GDDR6 PHY

Overview

High-performance IP for graphics, AI/ML, and automotive products

The silicon-proven GDDR6 PHY and controller IP showcase leading-edge BER, BIST, and RAS capabilities. GDDR6 offers significantly more performance than the fastest speed of DDR5 at a moderate cost, making it ideal for high-bandwidth applications. Cadence’s unique, single-vendor GDDR6 IP solution speeds up integration and reduces interoperability risk.

Key Features

Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
DFI PHY Independent Mode for initialization and training
Adaptive and continuous timing recovery
Internal and external datapath loop-back modes
Transmit crosstalk cancelation of immediate neighbors
Per-bit DFE, CTLE, and FFE equalization

Benefits

Proven: Silicon characterization reports available in multiple process technologies and foundries
Low Latency: For data-intensive applications
Low Power and Area: Industry-leading PPA based on advanced architecture and implementation
Low BER: Supporting standard PCB materials
Reliable: Maximum system margin with advanced clocking and I/O architectures
Future proof: Cutting edge technology with the latest GDDR protocols and the highest data rates

Block Diagram

Technical Specifications

Maturity

Available on request

TSMC

Pre-Silicon: 5nm

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