IP Catalog > FinFET

FinFET IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (723)
Compare 723 IP from 22 vendors (1 - 10)
  • PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
    • High-performance PHY for data center applications
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Multi-protocol support for application flexibility
  • 112G-XSR Pam4 for TSMC 7nm FinFET CMOS
    • TSMC 7nm FinFET CMOS Process
    • 112G PAM4 interface compatible to LR and VSR
    • Eight-lane compact footprint for high-density designs
    • Integrated BIST capable of producing and checking PRBS
  • PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
    • DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
    • Low active and standby power consumption, supports L1 sub-states standby power management
    • Extensive set of isolation, test modes, and loopbacks including APB and JTAG
    • Supports lane aggregation and bifurcation
  • TSMC CLN3FFP HBM4 PHY
    • IGAHBMZ03A is a High Bandwidth Memory 4 Physical  Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
    • Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
    Block Diagram -- TSMC CLN3FFP HBM4 PHY
  • MIPI D-PHY℠ v2.5 IP Core
    • This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and power dissipation, and is available for a range of foundry processes.
    • This IP delivers 6 Gbps per lane for a max throughput of 24 Gbps in D-PHY℠ mode, and 6 Gsps per trio for a max throughput of 41.04 Gbps in C-PHY℠ mode.
    Block Diagram -- MIPI D-PHY℠ v2.5 IP Core
  • MIPI C-PHY℠ v2.0 + D-PHY℠ v2.5 Combo IP Core
    • This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and power dissipation, and is available for a range of foundry processes.
    • This IP delivers 6 Gbps per lane for a max throughput of 24 Gbps in D-PHY℠ mode, and 6 Gsps per trio for a max throughput of 41.04 Gbps in C-PHY℠ mode.
    Block Diagram -- MIPI C-PHY℠ v2.0 + D-PHY℠ v2.5 Combo IP Core
  • USB 2.0 nanoPHY - UMC 65SP, OTG
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 nanoPHY - UMC 65SP, OTG
  • USB 2.0 picoPHY - UMC 40LP25, OTG
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 picoPHY - UMC 40LP25, OTG
  • USB 2.0 femtoPHY - UMC 28HPC18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - UMC 28HPC18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 picoPHY - UMC 28HLP18 x1, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 picoPHY - UMC 28HLP18 x1, North/South (vertical) poly orientation
×
Semiconductor IP