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FinFET IP

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Search (420)
Compare 420 IP from 22 vendors (1 - 10)
  • 1.8V general purpose I/O for 4nm FinFET
    • Enable higher voltage operation, beyond the foundry IO levels
    • Easily replace existing I/O cells
    • Integrated scalable ESD protection
    • Bias circuit can be shared with multiple I/Os
    Block Diagram -- 1.8V general purpose I/O for 4nm FinFET
  • PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
    • High-performance PHY for data center applications
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Multi-protocol support for application flexibility
  • 112G-XSR Pam4 for TSMC 7nm FinFET CMOS
    • TSMC 7nm FinFET CMOS Process
    • 112G PAM4 interface compatible to LR and VSR
    • Eight-lane compact footprint for high-density designs
    • Integrated BIST capable of producing and checking PRBS
  • PHY for PCIe 5.0 and CXL for TSMC 5nm FinFet
    • High-performance PHY for data center applications
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Multi-protocol support for application flexibility
  • Small area rail clamp for FinFET
    • Power clamp ESD solutions
    • Rail clamp ESD protection
    • 0.75V domain
  • PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
    • DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
    • Low active and standby power consumption, supports L1 sub-states standby power management
    • Extensive set of isolation, test modes, and loopbacks including APB and JTAG
    • Supports lane aggregation and bifurcation
  • ComputeRAM
    • Available as a 18 kB macro in GlobalFoundries 22FDX process; - Memory Compiler and FinFET variants under development
    • Low power sleep mode with data retention
    • Built using proven foundry SRAM bit cells, fully CMOS, strictly obeys foundry DFM/DRC rules
    • Bit-accurate computation
    Block Diagram -- ComputeRAM
  • Bi-Directional LVDS with LVCMOS
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    • Operates over 2Gbps and up to 3Gb/s in some processes
    • Trimmable on-die termination, can be enabled while Tx is operating for better signal integrity
    Block Diagram -- Bi-Directional LVDS with LVCMOS
  • Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
    • eDP version 1.4a / DP version 1.4 compliant transmitter
    • Supports HDCP1.4 and HDCP2.2(Optional)
    • Supports Forward Error Correction (Optional)
    • Consists of configurable (4/2/1) link channels and one AUX channel
    Block Diagram -- Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
  • LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
    • TSMC 3nm FinFET process
    • Input voltage: 1.2 V
    • Output voltage range: 0.45 V to 0.9 V
    • Vout adjustable in 50 mV increments
    Block Diagram -- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
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