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Search (731)
Compare 731 IP from 24 vendors (1 - 10)
  • 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
    • The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
    • Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
    Block Diagram -- 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
  • PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
    • High-performance PHY for data center applications
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Multi-protocol support for application flexibility
  • 112G-XSR Pam4 for TSMC 7nm FinFET CMOS
    • TSMC 7nm FinFET CMOS Process
    • 112G PAM4 interface compatible to LR and VSR
    • Eight-lane compact footprint for high-density designs
    • Integrated BIST capable of producing and checking PRBS
  • PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
    • DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
    • Low active and standby power consumption, supports L1 sub-states standby power management
    • Extensive set of isolation, test modes, and loopbacks including APB and JTAG
    • Supports lane aggregation and bifurcation
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY
  • 12-bit ADC on Samsung 8nm LN08LPP
    • The sf_adc0802x_ln08lpp_306011 is a 1.8V/0.75V dual supply-voltage 16-ch 12-bit analog-to-digital converter (ADC) that supports conversion rate (FS) up to 1MS/s, designed in 8nm CMOS FinFET process.
    • It consists of a 16-to-1 analog input MUX, a successive approximation (SAR) type monolithic ADC, a clock generator, and level-shifters for low voltage digital interface.
    Block Diagram -- 12-bit ADC on Samsung 8nm LN08LPP
  • 12-bit ADC on Samsung 4nm LN04LPE
    • ADC0401X is a 1.2-V/0.75-V dual supply voltage 16-channel 12-bit Analog-to-Digital Converter (ADC) that supports conversion rate (FS) up to 1 MS/s, designed in 4-nm CMOS FinFET process.
    Block Diagram -- 12-bit ADC on Samsung 4nm LN04LPE
  • USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
  • USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N4P 1.2V, North/South Poly Orientation
  • USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
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