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Fault-tolerant processor IP

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Compare 4 IP from 2 vendors (1 - 4)
  • 32-bit Embedded RISC-V Functional Safety Processor
    • The EMSA5-FS is a processor core designed for functional safety.
    • The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing the RISC-V Instruction Set Architecture (ISA).
    Block Diagram -- 32-bit Embedded RISC-V Functional Safety Processor
  • RISC-V Application Processor
    • The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture.
    • The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel.
    Block Diagram -- RISC-V Application Processor
  • 32-bit SPARC V8 processor
    • The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellites and scientific instruments.
    • The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and particularly suitable for system-on-a-chip (SOC) designs.
    Block Diagram -- 32-bit SPARC V8 processor
  • Configurable AMBA bus SoC platform
    • Robust and fully synchronous single-edge clock designs
    • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
    • Fault-tolerant and SEU-proof version
    • Symmetric Multi-processor support (SMP)
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