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Fault-tolerant processor IP

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Compare 5 IP from 2 vendors (1 - 5)
  • Fault-tolerant 32-bit SPARC V8 processor
    • Register file SEU error-correction of up to 4 errors per 32-bit word
    • Cache memory error-correction of up to 4 errors per tag or 32-bit word
  • 32-bit Embedded RISC-V Functional Safety Processor
    • The EMSA5-FS is a processor core designed for functional safety.
    • The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing the RISC-V Instruction Set Architecture (ISA).
    Block Diagram -- 32-bit Embedded RISC-V Functional Safety Processor
  • RISC-V Application Processor
    • RISC-V 64IMC, with AFDN (ie GCN) to be released
    • RISC-V standard PLIC
    • RISC-V standard PMP (physical memory protection)
  • Configurable AMBA bus SoC platform
    • Robust and fully synchronous single-edge clock designs
    • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
    • Fault-tolerant and SEU-proof version
    • Symmetric Multi-processor support (SMP)
  • Single- and double-precision IEEE-754 floating-point unit
    • IEEE-754 compliant, supporting all rounding modes and exceptions
    • Operations: add, subtract, multiply, divide, square-root, convert, compare, move, abs, negate
    • Data formats: single and double precision (32- and 64-bit floats)
    • Fully pipelined, 3 clock cycles latency for all operations except divide and square-root
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Semiconductor IP