Embedded monitoring IP

Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
Status Monitors provides embedded logic analyzer capability
Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.

KMX 100G MAC and PCS core, which consists of media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard.
The core implements RS FEC as defined in IEEE 802.3bj Clause 91 with independent bit error detection and bit error correction.

KMX 40G MAC and PCS core, which including media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard.
The core supports RS FEC as defined in Clause 74 IEEE 802.3 with independent error bit detection and error bit correction.

Pre-integrated CPU
Full suite of hardware-accelerate cryptographic engine (Meet EVITA-Full requirements)
Complete SDK with APIs for HSM operations to support chip security applications.
MailBox Interface to facilitate communication between the main system and HSM.

Service Layer receives messages from the Tessent Embedded Analytics message infrastructure
AXI Bus Communicator driver takes care of low-level HW control, separating kernel driver functionality and the user-space application
Message Codec allows services to access on-the-fly encode and decode for Tessent Embedded Analytics messages, simplifying development of efficient embedded applications
Intercom Layer provides direct access to the analytics modules in the Tessent Embedded Analytics system.

Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
Status Monitors provides embedded logic analyzer capability
Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.

Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
Status Monitors provides embedded logic analyzer capability
Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.

Provides a communication path for embedded software to pass data to the debug host for analysis and visualization
Watchpoints can be inserted in software with minimal effect on runtime code
Can pass out parameters from SoC to debugger when a watchpoint is reached. This increases visibility and makes it possible to pass out larger data structures without calling on trace

Analyzes on-chip signals and interfaces.
Measure the performance and verify the functionality
“Logic-analyzer” type visibility of internal signals not normally detectible off-chip
Run-time configurable

Full transaction and trace-level visibility of traffic
Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency

Embedded Monitoring IP