Tessent Automotive IC debug and optimization

Overview

Vehicles are becoming highly complex systems approaching billions of lines of code.

Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs. Leveraging embedded non-intrusive instrumentation such as bus monitors, NoC monitors, and CPU debug modules, debug and software engineers can observe what’s happening in the design when operational software is running on the system. The instruments enable full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering.

All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.

Key Features

Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
Status Monitors provides embedded logic analyzer capability
Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
Static instrumentation provides a nonintrusive mechanism for conde instrumentation.
Direct Memory Access (DMA) analytic module provide direct memory access to system memory from debug host.

Benefits

Observe if your Automotive SoC with massive parallelism behaves as it was meant to
Slash your escalating SoC validation costs
Identify and resolve errors and bugs significantly faster compared to traditional software-only solutions
Root-cause performance degradations and memory corruption

Deliverables

Parameterized soft core (Verilog RTL)
Available UVM verification IP
Optional Tessent SystemInsight IDE software
Optional Tessent Embedded SDK software development kit

Technical Specifications

Maturity

In silicon

Availability

Now

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