DisplayPort 2.1 IP
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17
IP
from 8 vendors
(1
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10)
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HDMI 2.1/ DisplayPort 2.1 Tx PHY TSMC N3P 1.2V, North/South Poly Orientation
- HDMI 2.1 TX IP solution includes PHYs, controllers, HDCP embedded security modules, and verification IP
- Compliant with the HDMI 2.1, 2.0, 1.4, and HDCP 2.3, 1.4 specifications
- Support for key HDMI 2.1 features such as fixed-rate link capable of 48Gbps aggregate bandwidth, enhanced
- Metadata packets including dynamic HDR, eARC, auto low-latency mode, and variable refresh rate
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HDMI 2.1/ DisplayPort 2.1 Tx PHY SS SF4X, North/South Poly Orientation
- HDMI 2.1 TX IP solution includes PHYs, controllers, HDCP embedded security modules, and verification IP
- Compliant with the HDMI 2.1, 2.0, 1.4, and HDCP 2.3, 1.4 specifications
- Support for key HDMI 2.1 features such as fixed-rate link capable of 48Gbps aggregate bandwidth, enhanced
- Metadata packets including dynamic HDR, eARC, auto low-latency mode, and variable refresh rate
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VESA Display Stream Compression (DSC) IP Core
- Supports Versions 1.1, 1.2 and 1.2a
- Supports RGB and YCbCr color spaces
- 1-to-8 slice support
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WiGig Wireless Display Codec
- WDE / WiGig H.264 Codec IP
- WiGig H.264 codec IP is designed to be integrated into a WiGig device, providing:
- * high-performance high-quality H.264 video compression,
- High 4:4:4 Intra Profile, support 8/10/12 bits
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DSC 1.2b Decoder
- Compliant with the VESA DSC 1.2b
- Backward compatible with the VESA DSC 1.1
- Supports all DSC 1.2b mandatory and optional coding schemes
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DSC 1.2b Encoder
- Compliant with the VESA DSC 1.2b
- Backward compatible with the VESA DSC 1.1
- Supports all DSC 1.2b mandatory and optional coding schemes
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VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
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VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
