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DSC Decoder IP

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Compare 22 IP from 10 vendors (1 - 10)
  • VESA DSC Decoder IIP
    • Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
    • Full DSC Decoder functionality.
    • Supports below coding schemes,
    • Modified Median-Adaptive Prediction (MMAP)
    Block Diagram -- VESA DSC Decoder IIP
  • DSC Decoder
    • Compliant with the VESA DSC 1.2a standards
    • Perform encoding
    • Support MMAP, BP, MPP and ICH
    Block Diagram -- DSC Decoder
  • VESA DSC Decoder
    • VESA Display Stream Compression (DSC) 1.2b compliant
    • Supports all DSC 1.2b mandatory encoding mechanisms: MMAP, BP, MPP, and ICH
    • Output buffering compatible with transport stream over video interfaces
    • Configurable maximum display resolution
    • Configurable compressed bit rate, in increments of 1/16 bpp
    • 8, 10, 12, 14, and 16 bits per video component
    Block Diagram -- VESA DSC Decoder
  • VESA DSC V1.2 Decoder
    • Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
    • It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications.
    Block Diagram -- VESA DSC V1.2 Decoder
  • VESA DSC V1.2 Decoder
    • Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
    • It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.
    Block Diagram -- VESA DSC V1.2 Decoder
  • VESA DSC 1.2a Decoder
    • Compliant with the VESA DSC 1.2a and 1.1 specifications
    • Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
    • Supports the latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
    • Configurable IP delivers low-power and small area
    Block Diagram -- VESA DSC 1.2a Decoder
  • DSC 1.2b Decoder
    •  Compliant with the VESA DSC 1.2b
    •  Backward compatible with the VESA DSC 1.1
    •  Supports all DSC 1.2b mandatory and optional coding schemes
    Block Diagram -- DSC 1.2b Decoder
  • Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
    • The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standard.
    • It supports decoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits per component color depths.
    • The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video decoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon.
    Block Diagram -- Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
  • Display Stream Compression (DSC 1.2) Decoder
    • The Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from 480 to 8K.
    • The core supports 8, 10, 12, 14 or 16 bits per pixel using either RGB or YCbCr in 4:4:4 or 4:2:2 format.
    • The DSC Decoder core integrates industry standard interfaces for host configuration and control, data input, and video output.
    Block Diagram -- Display Stream Compression (DSC 1.2) Decoder
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Semiconductor IP