Ddr sdram phy IP

Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR5/4x/4/3/2 SDRAM Memory Controller IP across a broad range of process technologies.

Dolphin's hardened DDR4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 4266 Mbps.
It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin's DDRx and LPDDRx SDRAM Memory Controller IP.

Compatible with JEDEC standard DDR2/DDR3/LPDDR (or Mobile DDR)/ /LPDDR2/LPDDR3 SDRAMs
Operating range of 100MHz (200Mb/s) to 533MHz(1066Mb/s) in DDR2/DDR3/LPDDR2/LPDDR3 modes
Operating range of DC to 200MHz in Mobile DDR mode
PHY Utility Block (PUBL) component

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM
The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA IP core work in conjunction with the ALTMEMPHY physical interface IP function
The controllers offer a half-rate interface and a full-rate interface to the customer application logic
For exact device support, please refer to the user guide.

The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DDR3/DDR4 SDRAM memories.
The synthesizable RTL (ddr_phy_top) provides control functions such as initialization, SDRAM interface training, impedance calibration and programmable configuration controls.

The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/ RDIMM/ LRDIMM/ UDIMM DDR5 devices
It is optimized for low-power and high-speed applications with robust timing and small silicon area
It supports all JEDEC DDR5/4 SDRAM components in the market

Supports JEDEC SDRAM standards including LPDDR4 (1.1V), LPDDR4x (0.6V), LPDDR5/5x (0.5V)
Supports data rates up to 4,266 Mbps LPDDR4/LPDDR5 and up to 8,533 Mbps LPDDR5x
Support for 16, 32 and 64-bit operation

Support for JEDEC standard DDR2, DDR3/3L/3U, LPDDR, and LPDDR2 SDRAMs
When combined with a Synopsys Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution
Scalable architecture that supports from 0 to 1066 Mbps
DFI 2.1 interface to controller

Support for JEDEC standard LPDDR2, LPDDR3, and DDR3 SDRAMs
Scalable architecture that supports data rates up to DDR3-2133
Support for DIMMs
Delivery of product as a hardened mixed-signal macrocell components allows precise control of timing critical delay and skew paths

When combined with a Synopsys DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
Support for DDR3L (1.35V DDR3)
Support for DDR2 and DDR3 DIMMs

DDR SDRAM PHY IP