The DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM memories. The DDR3/2 PHY IP supports the entire range of DDR3 SDRAM speeds, from DDR3-800 through DDR3-2133, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. The PHYs are compiled into a hard macro optimized for specific foundry nodes. Each DDR3/2 PHY is constructed from the following libraries of components: the application-specific SSTL I/O library, a single address/command macroblock and multiple byte-wide data macro blocks instantiated as many times as required to accommodate the memory channel width. Finally, the DDR3/2 PHY includes a PHY Utility Block (PUB) that is supplied as soft IP. The PUB contains the circuitry to calibrate and maintain the calibration of the DDR3/2 PHY’s delay lines, provide voltage and temperature-based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.
A key component of the DDR3/2 PHY is the extensive in-system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.
