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Cache Controller IP

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Compare 175 IP from 30 vendors (1 - 10)
  • 64-bit CPU Core with Level-2 Cache Controller
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    Block Diagram -- 64-bit CPU Core with Level-2 Cache Controller
  • AHB Cache Controller
    • The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master interface to the memory subsystem. The processor and memory interfaces are natively AHB5 and can easily be reduced to AHB-lite. 
    • The cache controller core supports a four-way associative cache memory and implements a Least Recently Used (LRU) replacement policy.
    Block Diagram -- AHB Cache Controller
  • CXL 3 Controller IP
    • The CXL 3 Controller IP is designed to support dual-mode operation, allowing dynamic selection between host and device modes.
    • It connects to standard 64GT/s PHYs through the PIPE 6.x interface and supports high data rates across various link widths.
    Block Diagram -- CXL 3 Controller IP
  • CXL CONTROLLER IIP
    • Compliant with CXL 1.0/1.1 Specifications
    • Supports Native PCIe mode and below features as defined in the PCIe specification
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0
    • PIPE interface
    Block Diagram -- CXL CONTROLLER IIP
  • CCIX 32G Premium Controller with AMBA bridge II
    • Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
    • Supports all required features of the PCIe 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
    • Choice of datapath widths (128-bit, 256-bit, or 512-bit)
    • Supports cache-coherency as defined by the CCIX standard
    Block Diagram -- CCIX 32G Premium Controller with AMBA bridge II
  • CCIX 32G Premium Controller II
    • Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
    • Supports all required features of the PCIe 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
    • Choice of datapath widths (128-bit, 256-bit, or 512-bit)
    • Supports cache-coherency as defined by the CCIX standard
    Block Diagram -- CCIX 32G Premium Controller II
  • CXL 3.1 Controller
    • Ultra-low Transmit and Receive latency
    • Internal data path size automatically scales up or down (256, 512 or 1024 bits) based on max. link speed and width for optimal throughput
    • Supports backwards compatibility to PCIe 6.1
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%
    • Loopback Mode support at DLL for CXL.mem and CXL.cache protocols
    • Merged Replay and Transmit buffer enables lower memory footprint
    Block Diagram -- CXL 3.1 Controller
  • Highest performance Six-wide, out-of-order core with a shared cluster cache enabling up to a 32-core cluster
    • Full support for the RVA22 RISC-V profile specification and Vector 1.0 and Vector Crypto for enabling 64-bit apps processors running feature rich OS stacks such as Linux and Android.
    • Breakthrough RISC-V performance
    • >12 SpecINT2k6/GHz (P870 Processor)
    • P800-Series Architectural Features
  • CXL 3.0 Dual Mode Controller
    • Compliant to CXL spec V3.X/V2.X.
    • Compliant to PCIE spec 6.0/5.0.
    • CPI Interface support.
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