CCSDS AR4JA LDPC Encoder Decoder IP
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CCSDS AR4JA LDPC Decoder & Encoder
- The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4).
- To obtain high throughput, two different levels of parallelism are carried out; 128 check nodes and 6 variable nodes which are processed at the same time.
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CCSDS AR4JA LDPC Encoder & Decoder
- Support for code rates 1/2, 2/3, and 4/5
- Uncoded block sizes of 1024, 4096,band 16384 bits
- Compliant with “TM Synchronization and Channel Coding, Recommended Standard, CCSDS 131.0-B-3, Blue Book, September 2017”
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CCSDS AR4JA LDPC Encoder and Decoder with code rates 1/2, 2/3, 4/5 and block sizes 1K, 4K, 16K
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources