The CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rates 1/2, 2/3 and 4/5, block lengths 1024, 4096 and 16384 are specially designed for deep-space missions, but the excellent error correction performance makes it the ideal fit for further applications with highest demands on forward error correction.The IP cores are available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip).
CCSDS AR4JA LDPC Encoder & Decoder
Overview
Key Features
- Support for code rates 1/2, 2/3, and 4/5
- Uncoded block sizes of 1024, 4096,band 16384 bits
- Compliant with “TM Synchronization and Channel Coding, Recommended Standard, CCSDS 131.0-B-3, Blue Book, September 2017”
Benefits
- Key benefits of the decoder are:
- Gains of up to 3 dB compared to Viterbi decoders
- Low-power and low-complexity design
- Layered LDPC decoder architecture, for convergence
- behavior that is twice as fast as non-layered LDPC decoders
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
- Optional fixed number of iterations for fixed latency of blocks with the same code rate and block length
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
- Collection of statistic information (number of iterations, decoding success, number of modified bits)
- Key benefits of the encoder are:
- High-throughput, low-latency encoder core
- Low-power and low-complexity design
Applications
- Near-Earth and Deep-Space communication.
- Space links communication.
- Space internetworking services.
- Further High-performance Applications
Deliverables
- VHDL source code or synthesized netlist
- HDL simulation models e.g. for Aldec’s Riviera-PRO
- VHDL testbench
- Bit-accurate Matlab, C or C++ simulation model
- Comprehensive documentation