BCH Decoder IP
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45
IP
from 16 vendors
(1
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10)
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DVB-S2X Wideband LDPC BCH Decoder
- Improved performance
- Improved efficiency w.r.t. Shannon’s limit
- Finer gradation of code rate and SNR
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DVB-C2 LDPC/ BCH Decoder
- Irregular Parity Check Matrix
- Layered Decoding
- Minimum Sum Algorithm
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UltraFast BCH Decoder
- BCH codes are widely used where bit errors are scattered randomly within the codeword. The Ultrafast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, tt achieves outstanding data rates.
- The design can be parameterized at design-time to support different codeword sizes and code rates. Latency can be adjusted by insertion or removal of pipeline register stages.
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DVB-T2 Demodulator and LDPC/ BCH Decoder
- DVB-T2 EN302 755 V1.2.1, Rev.9 compliant
- Supports IF input
- Single input – Single output (SISO)
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DVB-S2 LDPC BCH Decoder and Encoder
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Soft decision decoding
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DVB-S2X LDPC BCH Decoder and Encoder
- Improved performance
- Improved efficiency w.r.t. Shannon’s limit
- Finer gradation of code rate and SNR
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BCH Decoder IP
- BCH decoder compliant with the DVB-T2/S2 standard.
- Available for Altera/Xilinx FPGA or ASIC implementation.
- High speed design.
- BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
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DVB-C2 Receiver (including LDPC and BCH decoder)
- Compliant with ETSI 302 769 (DVB-C2).
- Support for short blocks (16200 bits) and long blocks (64800 Bits).
- Support for all modulation schemes (16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM).
- Support for all interleaving schemes of all modulation schemes.
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BCH Decoder
- BCH decoder compliant with the DVB-T2/S2 standard.
- Available for Altera/Xilinx FPGA or ASIC implementation.
- High speed design.
- BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
- Area and power optimized implementation.
