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AI Inference Accelerator IP

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  • AI Accelerator
    • Independent of external controller
    • Accelerates high dimensional tensors
    • Highly parallel with multi-tasking or multiple data sources
    • Optimized for performance / power / area
  • AI Accelerator Specifically for CNN
    • A specialized hardware with controlled throughput and hardware cost/resources, utilizing parameterizeable layers, configurable weights, and precision settings to support fixed-point operations.
    • This hardware aim to accelerate inference operations, particulary for CNNs such as LeNet-5, VGG-16, VGG-19, AlexNet, ResNet-50, etc.
    Block Diagram -- AI Accelerator Specifically for CNN
  • NPU IP for Embedded AI
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded AI
  • High performance-efficient deep learning accelerator for edge and end-point inference
    • Configurable MACs from 32 to 4096 (INT8)
    • Maximum performance 8 TOPS at 1GHz
    • Configurable local memory: 16KB to 4MB
    Block Diagram -- High performance-efficient deep learning accelerator for edge and end-point inference
  • Edge AI Accelerator NNE 1.0
    • Minimum efforts in system integration
    • Speed up AI inference performance
    • Super performance for power sensitive application
    Block Diagram -- Edge AI Accelerator NNE 1.0
  • AI Accelerator (NPU) IP - 3.2 GOPS for Audio Applications
    • 3.2 GOPS
    • Ultra-low <300uW power consumption
    • Low latency
    Block Diagram -- AI Accelerator (NPU) IP - 3.2 GOPS for Audio Applications
  • AI Accelerator: Neural Network-specific Optimized 1 TOPS
    • Performance efficient 18 TOPS/Watt
    • Capable of processing real-time HD video and images on-chip
    • Advanced activation memory management
  • NPU / AI accelerator with emphasis in LLM
    • Programmable and Model-flexible
    • Ecosystem Ready
  • AI accelerator
    • Massive Floating Point (FP) Parallelism: To handle extensive computations simultaneously.
    • Optimized Memory Bandwidth Utilization: Ensuring peak efficiency in data handling. Our IP core’s design is fully parametrizable, allowing it to scale seamlessly and maximize efficiency based on the target architecture, thanks to our sophisticated scheduling and flow control logic.
  • Tensilica AI Max - NNA 110 Single Core
    • Scalable Design to Adapt to Various AI Workloads
    • Efficient in Mapping State-of-the-Art DL/AI Workloads
    • End-to-End Software Toolchain for All Markets and Large Number of Frameworks
    Block Diagram -- Tensilica AI Max - NNA 110 Single Core
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