7nm LPDDR5X PHY IP
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LPDDR5X Secondary/Slave (memory side!) PHY
- JEDEC standard LPDDR5X @ 8533Mbps (Mbits per second per pin)
- Flexible channel architecture – 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels – 64-bit support, supporting two x32 channels
- Support for byte-mode DRAM devices for high capacity systems
- ZQ Calibration
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LPDDR5X/5/4X/4 combo PHY at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE
