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3D I/O IP

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Search (15)
Compare 15 IP from 9 vendors (1 - 10)
  • 3D LUT Intel® FPGA IP
    • As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the 3D look-up table (LUT) Intel® FPGA IP provides an efficient solution for video color space and dynamic range conversions, chroma keying, and the creation of artistic effects.
    Block Diagram -- 3D LUT Intel® FPGA IP
  • OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
    • D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores.
    • It is the first IP to bring 3D graphics OpenGL ES 2.0 rendering (with some ES 3.0 / 3.1 extensions) to the FPGA and SoC world and – with offline-shader compilers – even into MCUs or low-end MPUs with small amounts of memory and bare-metal or RTOS operation systems.
    Block Diagram -- OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
  • OpenGL® ES2.0 compatible 3D graphics IP core
    • The smallest class 3D graphics IP core, 0.48mm² in silicon footprint
    • Full OpenGL ES 2.0 capability
    • Ultra-low power consumption
  • 3-D Audio Processing Core
    • The J5 is a core cell design of an application specific signal processor which performs both Trusurround(TM) and SRS® 3-D audio virtualization processing in a single design.
    • The 3-D processing allows users to enjoy benefits of a multi-channel sound source with only two reporduction channels. 
    Block Diagram -- 3-D Audio Processing Core
  • NVMe SSD Controller Platform
    • The PCIe-NVMe SSD controller platform is compliant with NVM Express 1.2 specification and targets for both enterprise and client SSD markets.
    • It features YEESTOR's NVMe controller core and LDPC error correction core to enable low-power and cost-effective SSD controllers that support 1x/1y/1z MLC/TLC and 3D NAND.
    Block Diagram -- NVMe SSD Controller Platform
  • TSMC N3P Source Sync 3DIO PHY
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N3P Source Sync 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N3P 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
  • TSMC N5 Source Sync 3DIO Library
    • Optimized for heterogeneous integration in 3D stacking
    • Enabling designers the flexibility and scalability to accelerate multi-die integration
    • Optimal PPA architected to supporting 2.5D and 3D packages
    • Versatile offering tuned for optimal use scenarios, including:
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Semiconductor IP