16g ucie IP

Compare 6 IP from 4 vendors (1 - 6)

PCIe 4.0 Controller
- PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5G/5G/8G/16G.
- PCIe Controller support dual mode (ROOT mode or Endpoint mode).
- PCIe Controller’s interface with PHY is PIPE 4.0 interface and the PCIe Controller’s interface with application layer is the AXI4.0 interface, and it also has a APB bus for register access.
- The Lane number is configable, it can support X1, X2, X4 lanes.
16G PHY in TSMC (N7) for Automotive
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Supports x1, x2, x4, x8, and x16 hard macro configurations
- Lane margining at the receiver
PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 22nm
- Duplex lane configurations of x2, x4, and x35
- Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
- Multiple lanes transceiver with data rate from 1Gbps to 16Gbps
- Transceiver version including both receiver and transmitter
- Transmitter only version
- 40bit/32bit/20bit/16bit selectable parallel data bus
16G PHY in TSMC (28nm, 16nm, 12nm, N7, N6)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Supports x1, x2, x4, x8, and x16 hard macro configurations
- Lane margining at the receiver
16G PHY in Samsung (14nm, 11nm)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Supports x1, x2, x4, x8, and x16 hard macro configurations
- Lane margining at the receiver

16G UCIe IP