14nm FinFET Phy IP
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27
IP
from 4 vendors
(1
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10)
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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
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Globalfoundries 12nm MIPI D-PHY V1.2@2.5GHz
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
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Globalfoundries 12nm MIPI D-PHY Rx only V1.2@2.5GHz
- Available in various foundry processes
- No external (off-chip) components required
- Can be ported to other processes.
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Globalfoundries 12nm MIPI D-PHY Tx only V1.2@2.5GHz
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
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Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
- TSMC12nm FFC
- IEEE 802.3u auto-negotiation, supporting 100Base-TX and 10BASE-T networks over twisted-pair cable in full-duplex or half-duplex mode
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MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
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MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
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MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes