14nm FinFET Phy IP
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27
IP
from 4 vendors
(1
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10)
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MIPI D-PHY Tx-Only 4 Lanes in TSMC (16nm) for Automotive
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Tx-Only 4 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Tx-Only 4 Lanes in GF (12nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Tx-Only 2 Lanes in TSMC (16nm) for Automotive
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Rx-Only 4 Lanes in GF (28nm, 12nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
-
MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
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MIPI D-PHY Bidirectional 4 Lanes in TSMC (40nm, 28nm, 16nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes
-
MIPI D-PHY Bidirectional 2 Lanes in TSMC (40nm, 28nm, 16nm)
- Compliant with the MIPI D-PHY specification
- Fully verified hard macro
- Up to 2.5 Gb/s per lane
- Aggregate throughput up to 10 Gb/s in 4 data lanes