VPU R2.6 on Artix 7 200T

Overview

Video Processing Unit IP

The VPU IP is a video processing system that is suitable for high-speed and high resolution video systems. It currently supports HDMI full-HD (1920x1080p) input and output interfaces, and can be used in various video processing and video transport applications. The VPU IP is able to perform multiple video processing algorithms within 60 fps (16.67 ms). This high-speed feature allows the IP to have video edge enhancement and real-time at-speed video sharpening.

The VPU IP is shipped in post-synthesis netlist form, and currently supports Xilinx FPGA
devices. Some core features and advantages are listed in the Features section below.

Key Features

  • Video processing system suitable for high-speed, high resolution video systems
  • HDMI Full-HD (1920x1080p) input & output at 60fps
  • High-speed processing at 60fps
    • Multiple algorithms complete within 16.67ms
    • HDMI passthrough (as a video repeater for video conferencing, etc.)
    • Video edge enhancement
    • Real-time at-speed video sharpening
  • Uses FPGA for parallel processing
    • Algorithms designed directly in FPGA hardware
    • Processor boot-up not required (IP ready to use immediately after chip power up)
  • Does not require external RAM (DDR3 / DDR4 / HBM)
  • AXI4-Stream and AXI4-Lite interface support for video transport and user configuration
  • 1 year free support, bugfixes, and upgrades
  • Zero to one month lead time for Xilinx devices

Benefits

  • VPU IP currently supports the following FPGA device families:
    • Xilinx Artix-7
    • Xilinx Zynq-7000
  • VPU IP currently supports the following development tools:
    • Xilinx Vivado
    • Synopsys VCS / Verdi Simulator
    • Intel Modelsim Simulator
    • Siemens Questa Simulator

Block Diagram

VPU R2.6 on Artix 7 200T Block Diagram

Applications

  • High-speed video transport
  • High-speed video pre-processing for AI applications

Deliverables

  • Post-synthesis netlists
    • VHDL stub file
    • Synthesisable EDIF netlist
    • Design constraints
  • Technical documentation
    • User Manual
    • Application Notes
  • Example designs
  • Variable length maintenance
    • Delivery of IP Core updates, minor and major changes
    • Delivery of documentation updates
    • Telephone & email support

Technical Specifications

Maturity
V2.6
Availability
Two Weeks
×
Semiconductor IP