The FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of system-on-chip (SoC) devices for mobile, automotive, consumer, enterprise, and other applications.
With FlexNoC 5 interconnect IP, engineers achieve reduced wiring congestion, larger timing margins, and lower power consumption, as well as improved productivity and design quality through a set of intuitive and powerful development tools.
FlexNoC is the ideal interconnect for SoC designs requiring higher performance with minimum area and power. Its flexible architecture makes it the right solution for interconnects with both low latency requirements and high throughput needs. FlexNoC provides support for the additional features that today's SoCs require, such as clock domain conversion, width conversion, security, and multi-protocol support. The product supports the AMBA (APB, AHB, AXI) protocols and OCP and can easily be extended to support proprietary protocols.
FlexNoC 5 Network-on-Chip (NoC)
Overview
Key Features
- FlexNoC Physical Awareness enables up to 5X faster physical closure over manual iterations to converge.
- Early physical awareness for faster convergence without re-designs Allows place and route tools a better starting point.
- Configurable link widths provide bandwidth where needed and allow a reduction in the number of wires required to interconnect IP cores.
- Fewer wires allow tighter placement of IP blocks and a smaller chip floorplan.
- NoC bandwidth regulation reduces average transaction latency in the entire chip while providing the lowest latency to the critical cores.
- The FlexNoC development tools enable interconnect configuration and seamless IP reuse and integration.
- FlexNoC includes a powerful automated testbench generator that creates and runs a comprehensive set of system and IP tests on the configured interconnect to achieve 100 percent coverage, along with functional coverage tests on all the system interfaces to ensure complete interoperability.
- Real-time on-the-fly traffic prioritization for bandwidth regulation
- Efficient SDRAM memory access scheduling
- Fully configurable internal network topology of link widths, arbiters, FIFOs, pipeline stages, rate adapters, traffic urgency, bandwidth regulators, and memory schedulers
- TLM 2.0 compliant SystemC simulation model generation
Benefits
- Physical Awareness for faster timing closure
- Higher margins
- Fewer wires
- Smaller die size
- Reduced power consumption
- Shorter schedules
- Automate interconnect setup and verification
Block Diagram
Video
Arteris FlexNoC 5 Physically Aware Network-on-Chip IP
Arteris unveils next-generation FlexNoC 5 physically aware network-on-chip IP. Get up to 5X faster physical convergence vs manual physical iterations and achieve PPA goals within schedule and budget constraints. Learn more at www.arteris.com/flexnoc
Applications
- Automotive, Mobility, Wireless, Consumer Electronics, IoT, Server, Networking and Industrial SoCs
Deliverables
- FlexNoC 5 Physically Aware Interconnect IP
- Configuration tools
- Automated testbench generator
- Documentation, training, and support.
- Safety Manual -- when licensed with the Functional Safety (FuSa) Option
Technical Specifications
Foundry, Node
all
Maturity
FlexNoC shipping in production chips
Availability
FlexNoC 4 available now, FlexNoC5 in early access programme