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Deskew PLL IP for UMC

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Compare 92 Deskew PLL IP for UMC from 3 vendors (1 - 10)
  • Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
    • Process portable
    • Proven (65nm to 3nm)
    • Full SCAN testable
    • Core voltage supply
  • UMC L28HPCLVT 28nm Deskew PLL - 220MHz-1100MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28HPCLVT 28nm Deskew PLL - 440MHz-2200MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28HPCLVT 28nm Deskew PLL - 880MHz-4400MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28EHVLVT 28nm Deskew PLL - 225MHz-1125MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28EHVLVT 28nm Deskew PLL - 450MHz-2250MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28EHVLVT 28nm Deskew PLL - 900MHz-4500MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28EHV 28nm Deskew PLL - 150MHz-750MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28EHV 28nm Deskew PLL - 300MHz-1500MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L28EHV 28nm Deskew PLL - 600MHz-3000MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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