LPDDR4 IP for TSMC
Welcome to the ultimate
LPDDR4 IP
for
TSMC
hub! Explore our vast directory of
LPDDR4 IP
for
TSMC
All offers in
LPDDR4 IP
for
TSMC
Filter
Compare
5
LPDDR4 IP
for
TSMC
from
2
vendors
(1
-
5)
Filter:
- 16nm
-
LPDDR4X multiPHY - TSMC16FFC18
- Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
- Support for data rates up to 4,267 Mbps (process dependent)
- Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
- PHY independent, firmware-based training using an embedded calibration processor
-
LPDDR4 multiPHY V2 - TSMC16FFC18
- Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
- Support for data rates up to 4,267 Mbps (process dependent)
- Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
- PHY independent, firmware-based training using an embedded calibration processor
-
LPDDR4X multiPHY - TSMC 16FFC18 for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
- Support for data rates up to 4,267 Mbps (process dependent)
- Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
- PHY independent, firmware-based training using an embedded calibration processor
-
LPDDR5/4/4X PHY - TSMC 16FFC
- Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
- Support for data rates up to 6400 Mbps
- Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
-
SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY - TSMC 16nm 16FFC,FF
- DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
- Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
- Built-in Gate Training, Read/Write Leveling, and VREF Training
- Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface