Serdes IP for TSMC
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- 16nm
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Low Power PCIe Gen3 PHY on TSMC CLN16FFC
- Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.133 mm2 total active area per lane
- Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
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Low Power 1-22G PCIe Gen4 / SAS4 PHY on TSMC CLN16FFC
- Industry leading low power PMA macro – 184mW per lane at 22.5Gbps (8.2mW/Gbps) and 108mW per lane at 16Gbps (6.75mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.145 mm2 total active area per lane
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
- Multi-orientation macros of 4, 8 and 16 lane SERDES are available for most common metal stacks
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SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm)
- Supports 1.25G to 10.3125Gbps data rates and compact die area
- Supports up to 25dB channel loss@ 5.15625GHz
- Supports RX loss-of-signal detection
- Supports X1, X2 and X4 lanes