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Compare 10 Other for TSMC from 4 vendors (1 - 10)
  • Camera Receiver - 10.0Gbps 8-Lane - TSMC 12FFC
    • The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP.
    • The CL12812M8RIP10000 is designed to support data rate in excess of maximum 10Gbps utilizing SLVS-EC ver.3.0 interface specification.
    Block Diagram -- Camera Receiver - 10.0Gbps 8-Lane - TSMC 12FFC
  • SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC
    • SLVS-EC ver.3.0 compliant
    • Data Rate: Up to 10Gbps / lane
    • Number of data lane: 8
    • Support input clock: 24MHz, 54MHz, 37.125MHz, 72MHz, 74.25MHz
    Block Diagram -- SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC
  • High voltage tolerant I/O
    • Scalable robustness
    • Area efficient
    • low capacitance option
  • Camera Receiver - 5.0Gbps 8-Lane - TSMC 12FFC, 6FFC
    • The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP.
    • The CL12812M8RIP5000 is designed to support data rate in excess of maximum 5Gbps utilizing SLVS-EC ver.3.0 BG3 interface specification

     

  • Small area rail clamp for FinFET
    • Power clamp ESD solutions
    • Rail clamp ESD protection
    • 0.75V domain
  • Analog I/O - low capacitance, low leakage
    • Scalable robustness
    • Area efficient
    • low capacitance option
  • LVDS TX PHY & Controller
    • Compatible with 900mV Vcom sub-LVDS standard
    • LVDS Display Serdes Interfaces directly to LCD Display Panels with Integrated LVDS
    • Suited for Display Resolutions Ranging from HVGA up to HD with Low EMI
    • Supports 4 data lanes and 1 clock lane mode, the data lane is extended according to customers.
  • LVDS TX Combo TTL PHY
    • Compatible with ANSI TIA/EIA-644 LVDS and IEEE Std1596.3-1996 standards
    • LVDS display SerDes interfaces directly to LCD display panels with integrated LVDS
    • Supports byte clock mode
    • Supports 7-bit parallel output per data lane in LVDS mode
  • LVDS RX PHY & Controller
    • Compatible with 900mV Vcom sub-LVDS standard
    • LVDS Display Serdes Interfaces directly to LCD Display Panels with Integrated LVDS
    • Suited for Display Resolutions Ranging from HVGA up to HD with Low EMI
    • Supports 4 data lanes and 1 clock lane mode, the data lane is extended according to customers.
  • XAUI PHY
    • ? 3.125-Gbps transmissions rate
    • ? Supports x4 configuration
    • ? Integrated regulator to support either 3.3-V or 2.5-V I/O power supply
    • ? Excellent performance margin and receiver sensitivity
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