IP Catalog > Foundries > TSMC > Analog IP > Clocking IP > PLL IP > Clock Generator PLL IP

Clock Generator PLL IP for TSMC

Welcome to the ultimate Clock Generator PLL IP for TSMC hub! Explore our vast directory of Clock Generator PLL IP for TSMC
All offers in Clock Generator PLL IP for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (13)
Compare 13 Clock Generator PLL IP for TSMC from 4 vendors (1 - 10)
Filter:
  • 7nm
  • 14GHz Integer-N High-Speed PLL
    • Type II hybrid Integer-N LC-PLL
    • Quadrature clocks at 14GHz and 7GHz
    • Fast locking
    Block Diagram -- 14GHz Integer-N High-Speed PLL
  • Fractional-N PLL for Performance Computing in TSMC N6/N7
    • Frequencies up to 4GHz
    • Low jitter (< 10ps RMS)
    • Small size (< 0.01 sq mm)
    Block Diagram -- Fractional-N PLL for Performance Computing in TSMC N6/N7
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • General Purpose Fractional-N PLLs
    • Low power, suitable for logic clocking applications
    • Extremely small die area, using a ring oscillator
    • Twelve bits fractional resolution
    Block Diagram -- General Purpose Fractional-N PLLs
  • High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
    • Fractional-N digital PLL architecture, using an LC-tank oscillator
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
  • Differential Clock Receiver to CML on TSMC CLN7FF
    • Differential IO clock receiver
    • CML differential output to chip core
    • Wide Ranges of input frequencies for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
  • Differential Clock Receiver on TSMC CLN7FF
    • Differential IO clock receiver
    • Single-ended output to chip core
    • Wide Ranges of input frequencies for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
  • TSMC CLN7FFLVT 7nm Clock Generator PLL - 600MHz-3000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN7FFLVT 7nm Clock Generator PLL - 300MHz-1500MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
  • TSMC CLN7FFLVT 7nm Clock Generator PLL - 1200MHz-6000MHz
    • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
    • Delivers optimal jitter performance over all multiplication settings.
    • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
    • Ideal for system clock generation, SerDes and video clock applications.
×
Semiconductor IP