subLVDS IP for SMIC
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subLVDS IP
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5
subLVDS IP
for SMIC
from 3 vendors
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Sub-LVDS receiver followed by 1:4 de-serializer
- Sub-low voltage differential signaling input: VID = 25mV MIN.
- Converts the subLVDS strobe/data (up to 960 Mbps throughput bandwidth) back into parallel 4 bits of CMOS data/strobe
- Power-down control function
- Full industrial operating temperature range -40 ~ +125 °C
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SMIC 55nm sub-LVDS Receiver
- Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
- 8 data channels / 2 clock channel integrated
- Maximum serial data rate per channel: 1Gbps
- Supports up to 16-bit CMOS parallel input (DVP input mode)
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SMIC 55nm sub-LVDS Receiver
- Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
- 10 data channels / 2 clock channel integrated
- Maximum serial data rate per channel: 1Gbps
- Supports up to 20-bit CMOS parallel input (DVP input mode)
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subLVDS I/O Pad Set
- Input receive sensitivity of 50mV peak differential (without hysteresis)
- Common mode range from 0.4V to 1.6V (limited by Power Supply)
- Powered by 1.8V I/O and 1.1V core supplies
- Power consumption: 3.4 mW max @ 800 MHz
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Mini LVDS Transmitter
- Selectable dual operation modes:
- Output offset voltage selectable from 0.8 – 1.5 V
- Output swing selectable from 200 – 500 mV
- Pre-emphasis selectable from 0 – 6 dB