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"13016" "keyfeatures" => "<ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li><li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li><li>AMBA 4 AXI and ACE-Lite bus interfaces</li><li>Memory data protection and memory address parity protection</li><li>Supports ATA/TAPI-7 specification</li><li>Supports power management features</li><li>Supports BIST loop-back modes</li><li>Supports up to 8 SATA devices per controller (configurable from 1 to 8 ports)</li><li>Native command queuing, streaming, and asynchronous notification</li><li>Port multiplier support with both command-based switch (CBS) and FIS-based switching (FBS)</li><li>Optional mechanical presence switch, cold presence detect, and activity LED support</li><li>Runs latest version of Windows or Linux AHCI software drivers “out of box”</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed- \n signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications. """ "overview_cn" => "" "partnumber" => "dwc_sata6gphy_smic" "priority" => 21 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li>\n <li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li>\n <li>AMBA 4 AXI and ACE-Lite bus interfaces</li>\n <li>Memory data protection and memory address parity protection</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY in SMIC (40nm, 28nm)" "shortdescription_cn" => "" "slug" => "sata-6g-phy-in-smic-40nm-28nm" "sortable_id" => 13016 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_sata6gphy_smic SATA 6G PHY in SMIC (40nm 28nm) Synopsys Inc." "text_low_priority" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using SATA interface mass storage. complete integrated is silicon-proven includes a comprehensive suite of configurable digital controllers high-speed mixed-\n signal PHYs verification IP. By providing from single vendor lowers integration risk by ensuring that all functions work together seamlessly. designers with high-performance extremely low in power area latency. has gone through extensive in-house third-party interoperability testing products shipping volume production. As leading supplier focused on delivering high-quality strict quality measures combined an expert technical support team enable accelerate time-to-market reduce next-generation storage applications. Compliant SATA/eSATA v3.3 AHCI v1.3 PIPE v4.3 specificationsAMBA 2.0 AHB AMBA 3 AXI subsystem interfacesAMBA 4 ACE-Lite bus interfacesMemory data protection memory address parity protectionSupports ATA/TAPI-7 specificationSupports management featuresSupports BIST loop-back modesSupports up 8 devices per controller (configurable 1 ports)Native command queuing streaming asynchronous notificationPort multiplier both command-based switch (CBS) FIS-based switching (FBS)Optional mechanical presence cold detect activity LED supportRuns latest version Windows or Linux software drivers “out box” """ "text_medium_priority" => "" "updated_at" => 1724088422 ] "highlight" => [] "highlights" => [] ] 1 => array:3 [ "document" => array:48 [ "asic.foundry" => array:4 [ 0 => "TSMC" 1 => "GLOBALFOUNDRIES" 2 => "SMIC" 3 => "UMC" ] "asic.foundry_node" => array:4 [ 0 => "TSMC_400" 1 => "GLOBALFOUNDRIES_400" 2 => "SMIC_400" 3 => "UMC_400" ] "asic.foundry_node_process" => array:5 [ 0 => "TSMC_400_G" 1 => "TSMC_400_LP" 2 => "GLOBALFOUNDRIES_400_LP" 3 => "SMIC_400_LL" 4 => "UMC_400_LP" ] "asic.node" => array:1 [ 0 => 400 ] "asic.node_foundry" => array:4 [ 0 => "400_TSMC" 1 => "400_GLOBALFOUNDRIES" 2 => "400_SMIC" 3 => "400_UMC" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1675927054 "id" => "17388" "keyfeatures" => "<ul><li>? 6-Gbps transmission rate through standard SATA cable </li><li>? Spread-spectrum clock (SSC) generation and absorption </li><li>? Programmable down-spread (+4,980 ppm through -4,980 ppm) </li><li>? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY </li><li>? Supports 20-bit interface at 300-MHz operation for SATA 6-Gbps data rate </li><li>? Supports 20-bit interface at 150-MHz operation for SATA 3-Gbps data rate </li><li>? Supports 20-bit interface at 75-MHz operation for SATA 1.5-Gbps data rate </li><li>? Integrated PHY includes transmitter, receiver, SSC generation, PLL, digital core, and ESD </li><li>? Programmable Rx equalization </li><li>? Supports collapsing of power supplies </li><li>? Supports x1/x2 configurations </li><li>? Supports legacy Half-rate mode for power-saving </li><li>? Integrated regulator to support both 3.3-V or 2.5-V I/O power supply </li><li>? Excellent performance margin and receiver sensitivity </li><li>? Robust PHY architecture that tolerates wide process, voltage, and temperature variations </li><li>? Low-jitter PLL technology with excellent supply isolation </li><li>? IEEE 1149.6 (JTAG) boundary scan </li><li>? Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester: </li><li>? Supports 6-Gbps, 3-Gbps, and 1.5-Gbps test modes </li><li>? Advanced, built-in diagnostics including on-chip sampling scope for easy debug </li><li>? Visibility and controllability of hard macro functions through programmable registers in the design </li><li>? Overrides on all ASIC side inputs for easy debug </li><li>? Access register space through simple 16-bit parallel interface </li><li>? Access register space through JTAG port</li></ul>" "keyfeatures_cn" => "" "keywords" => "SATA 6G" "logo" => "verisyno-66bb47b55ef5f.webp" "logo2" => "verisyno-66bb47b55ef5f.webp" "name" => "asic.node" "overview" => "The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SATA 6G applications. The SATA 6G PHY sata6g_pma_xN includes all the necessary logical, geometric, and physical design files to implement complete SATA 6G physical layer capability for 6-Gbps operation, connecting a host or device controller to a SATA system. The SATA 6G PHY supports the SATA 6-Gbps protocol and data rate, and is backward-compatible with SATA Gen I and Gen II operating at 1.5-Gbps and 3.0-Gbps data rates." "overview_cn" => "" "partnumber" => "SATA 6G PHY" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 486 "provider.name" => "VeriSyno Microelectronics Co., Ltd." "provider.object" => "{"id":486,"name":"VeriSyno Microelectronics Co., Ltd.","providerslug":"verisyno-microelectronics-co-ltd"}" "provider.priority" => 1 "provider.slug" => "verisyno-microelectronics-co-ltd" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>? 6-Gbps transmission rate through standard SATA cable</li>\n <li>? Spread-spectrum clock (SSC) generation and absorption</li>\n <li>? Programmable down-spread (+4,980 ppm through -4,980 ppm)</li>\n <li>? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY" "shortdescription_cn" => "" "slug" => "sata-6g-phy" "sortable_id" => 17388 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SATA 6G PHY VeriSyno Microelectronics Co. Ltd." "text_low_priority" => "The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution designed for single-chip integration into applications. sata6g_pma_xN includes all the necessary logical geometric and physical design files to implement layer capability 6-Gbps operation connecting host or device controller system. supports protocol data rate backward-compatible with Gen I II operating at 1.5-Gbps 3.0-Gbps rates. transmission through standard cable Spread-spectrum clock (SSC) generation absorption Programmable down-spread (+4 980 ppm -4 ppm) Fully clock-forwarded transceiver interface configurable using soft PMA above hard macro Supports 20-bit 300-MHz 150-MHz 3-Gbps 75-MHz Integrated transmitter receiver SSC PLL digital core ESD Rx equalization collapsing of power supplies x1/x2 configurations legacy Half-rate mode power-saving regulator support both 3.3-V 2.5-V I/O supply Excellent performance margin sensitivity Robust architecture that tolerates wide process voltage temperature variations Low-jitter technology excellent isolation IEEE 1149.6 (JTAG) boundary scan Built-in Self-Test (BIST) features production at-speed testing on any tester: test modes Advanced built-in diagnostics including on-chip sampling scope easy debug Visibility controllability functions programmable registers in Overrides ASIC side inputs Access register space simple 16-bit parallel JTAG port" "text_medium_priority" => "SATA 6G " "updated_at" => 1712895415 ] "highlight" => [] "highlights" => [] ] 2 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "SMIC" ] "asic.foundry_node" => array:1 [ 0 => "SMIC_140" ] "asic.foundry_node_process" => array:1 [ 0 => "SMIC_140_" ] "asic.node" => array:1 [ 0 => 140 ] "asic.node_foundry" => array:1 [ 0 => "140_SMIC" ] "blockdiagram" => "" "category.id" => array:3 [ 0 => 34 1 => 353 2 => 382 ] "category.name" => array:3 [ 0 => "SATA PHY IP" 1 => "PCI Serdes / PHY IP" 2 => "USB 3.0 PHY IP" ] "category.slug" => [] "created_at" => 1624953070 "id" => "15235" "keyfeatures" => "<ul><li>Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),</li><li>Backward compatible with 1.5Gbps, 3.0bps for SATA</li><li>Backward compatible with 2.5Gbps and 5Gbps for PCIe</li><li>Full compatible with PIPE4 interface specification</li><li>20bit/16bit selectable parallel data bus</li><li>Independent channel power down control</li><li>Programmable transmit amplitude and FFE</li><li>Implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss</li><li>Production test support is optimized through high coverage at-speed BIST and loopback</li><li>Integrated on-die termination resistors and IO Pads/Bumps</li><li>Support receiver detection, LFPS/OOB/Beacon signal generation and detection</li><li>Support Spread Spectrum clock generation(optional) and receiving</li><li>Embedded Primary & Secondary ESD Protection HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mA</li><li>Silicon Proven in SMIC 14SF+</li></ul>" "keyfeatures_cn" => "<ul><li>支持SATA3（6.0Gbps），USB3.0（5Gbps）和PCIe3（8.0Gbps），\r</li><li>向后兼容 1.5Gbps，SATA 为 3.0bps\r</li><li>向后兼容 2.5Gbps 和 5Gbps 的 PCIe\r</li><li>完全兼容 PIPE4 接口规范\r</li><li>20位/16位可选并行数据总线\r</li><li>独立的通道关断控制\r</li><li>可编程发射幅度和FFE\r</li><li>实现接收器均衡自适应CTLE和DFE，以补偿插入损耗\r</li><li>通过高覆盖率高速 BIST 和环回优化生产测试支持\r</li><li>集成片上端接电阻器和 IO 焊盘/凸块\r</li><li>支持接收器检测，LFPS / OOB /信标信号生成和检测\r</li><li>支持扩频时钟生成（可选）和接收\r</li><li>嵌入式初级和次级ESD保护HBM / MM / CDM / Latch-Up 2000V / 200V / 500V / 100mA\r</li><li>在SMIC 14SF+工艺中通过硅验证</li></ul>" "keywords" => "USB 3.0combo PHY, SATA 3.0, PCIe2.0, combo serdes, combo phy ip, usb combo phy in tsmc,USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serdesip" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => """ The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. \n USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP is a high performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. Combo PHY IP support multiple application including USB3.0 Super Speed (5GT/s), PCIE Gen1/Gen2/Gen3 (2.5GT/s/ 5GT/s/ 8GT/s) and SATA Gen1/Gen2/Gen3 (1.5GT/3GT/6GT) This IP includes two major blocks, PMA and PCS. PMA is an analog macro to perform serial to parallel and parallel to serial conversion. PMA includes three blocks, Transmitter, Receiver and SU (includes PLL, IVREF, etc.). PCS is a digital synthesis macro to perform PHY coding sub-layer function like 8bit/10bit, elastic buffer, comma detection and BERT loopback, it also includes a register interface to access internal control registers. """ "overview_cn" => """ 这个Combo PHY IP符合SATA 3.0规范的串行ATA（SATA），符合PCIe 2.0基本规范并支持PIPE接口规范PCIe，以及符合USB 3.0、USB 2.0（USB高速和全速）规范的USB。这个Combo PHY IP通过支持额外的PLL控制，参考时钟控制，和内置的电源门控控制来降低功耗。此外，这个PHY IP能够根据不同的功耗的需求进行客制化设计，拥有广泛的应用场景。 \r\n \r\n USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP 是高性能 SERDES IP，专为在低功耗下执行高带宽数据通信的芯片设计。这个Combo PHY IP支持多种传输速率，包括USB3.0Super Speed（5GT/s），PCIE Gen1 /Gen2 /Gen3（2.5GT/s / 5GT/s / 8GT/s）和SATA Gen1 / Gen2 / Gen3（1.5GT / 3GT / 6GT）这个Combo PHY IP由PMA和PCS组成，PMA用于执行串行到并行和并行到串行转换的模拟宏，包括三个模块，发射器、接收器和 SU（包括 PLL、IVREF 等）；PCS是用于执行PHY编码子层功能的数字合成宏，支持如8位/10位，弹性缓冲区，逗号检测和BERT环回等功能，此外，这个Combo PHY IP的交付件还包含寄存器接口来访问内部控制寄存器。 """ "partnumber" => "USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 14SF+" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),</li>\n <li>Backward compatible with 1.5Gbps, 3.0bps for SATA</li>\n <li>Backward compatible with 2.5Gbps and 5Gbps for PCIe</li>\n <li>Full compatible with PIPE4 interface specification</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+" "shortdescription_cn" => "USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP，在 SMIC 14SF+ 中经过硅验证" "slug" => "usb-3-0-pcie-3-0-sata-3-0-combo-phy-ip-silicon-proven-in-smic-14sf" "sortable_id" => 15235 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:2 [ 0 => 688 1 => 7 ] "taxo2" => array:3 [ 0 => 33 1 => 58 2 => 64 ] "taxo3" => array:3 [ 0 => 34 1 => 455 2 => 381 ] "taxo4" => array:2 [ 0 => 353 1 => 382 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.0/ PCIe SATA 3.0 Combo PHY IP in 14SF+ Silicon Proven SMIC T2M GmbH" "text_low_priority" => """ The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification support PIPE interface spec Universal Serial Bus (USB) the USB 2.0 (USB High-speed and Full speed) ATA (SATA) SATA Specification. Lower power consumption is achieved due to additional PLL control reference clock embedded gating control. Also since aforementioned low mode setting configurable widely applicable for various scenarios under different consideration consumption.\n USB Combo IP a high performance SERDES designed chips that perform bandwidth data communication while operating at consumption. multiple application including USB3.0 Super Speed (5GT/s) PCIE Gen1/Gen2/Gen3 (2.5GT/s/ 5GT/s/ 8GT/s) (1.5GT/3GT/6GT) This includes two major blocks PMA PCS. an analog macro serial parallel conversion. three Transmitter Receiver SU (includes IVREF etc.). PCS digital synthesis coding sub-layer function like 8bit/10bit elastic buffer comma detection BERT loopback it also register access internal registers. Support SATA3(6.0Gbps) USB3.0(5Gbps) PCIe3(8.0Gbps) Backward compatible 1.5Gbps 3.0bps SATABackward 2.5Gbps 5Gbps PCIeFull PIPE4 specification20bit/16bit selectable busIndependent channel down controlProgrammable transmit amplitude FFEImplemented equalization Adaptive-CTLE DFE compensate insertion lossProduction test optimized through coverage at-speed BIST loopbackIntegrated on-die termination resistors IO Pads/BumpsSupport receiver LFPS/OOB/Beacon signal generation detectionSupport Spread Spectrum generation(optional) receivingEmbedded Primary & Secondary ESD Protection HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mASilicon Proven in SMIC 14SF+ """ "text_medium_priority" => "USB 3.0combo PHY SATA 3.0 PCIe2.0 combo serdes phy ip usb in tsmc USB3.2 3.2 umc 28nm 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata serdesip" "updated_at" => 1681285923 ] "highlight" => [] "highlights" => [] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => 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1098662720 "id" => "679" "keyfeatures" => """ <ul>\r\n \t<li>Supports 1.5 Gb/s (Gen 1) and 3.0 Gb/s (Gen 2) serial data rate</li>\r\n \t<li>Compatible with Serial ATA II</li>\r\n \t<li>Utilizes 10-bit or 20-bit parallel interface to transmit and receive Serial ATA data</li>\r\n \t<li>Data and clock recovery from serial stream on the SATA bus</li>\r\n \t<li>Optional 8b/10b encode/decode and error indication</li>\r\n \t<li>Near-End and Far-End Loop-back Support</li>\r\n \t<li>Embedded Bit Error Rate Testing Through PBRS generation and detection</li>\r\n \t<li>Supports HOST and DEVICE controller applications</li>\r\n \t<li>OOB Signal Detection for COMWAKE, COMRESET/COMINIT and COMSAS</li>\r\n \t<li>COMMA & Squelch Detect Support</li>\r\n \t<li>Power Management Support for Slumber and Partial PM Modes.</li>\r\n \t<li>Calibrated Internal RX, TX Termination Resistors</li>\r\n \t<li>Support for Serial Attached SCSI SAS Mode</li>\r\n \t<li>Compliant with SATA PHY Interface Specification (SAPIS)</li>\r\n \t<li>Full low cost, low power CMOS Implementation</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "SATA Serial ATA IO PHY IP Transceiver SAS" "logo" => "softmixedsignal-66bb47641461c.webp" "logo2" => "softmixedsignal-66bb47641461c.webp" "name" => "asic.node" "overview" => """ SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling. It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, Comma detect for 8B/10B encoded data and Frame alignment functionalities. Digital controller interface is realized with a 10-bit parallel operation (Optional 20-bit Interface) that allows use of 150 MHz (300 MHz) reference Clock. The transceiver includes Signal Detect, COMRESET/COMINIT and COMWAKE Out-of-Band capability compliant with Serial ATA Specification requirements in addition to COMSAS Out-of-band Signal detection capability required by the Serial Attached SCSCI (SAS).\r\n \r\n SMS6000 complies with the latest version of the SAPIS standard both as a PHY Core IP and for discrete Transceiver implementations.\r\n \r\n SMS6000 implements the full requirements of Serial ATA 1.0a specification in terms of Power Management and Loopback functionality. Both Partial and Slumber power management modes are fully supported both in the digital portion and the AFE of the PHY for maximum power efficiency. Also all the Loopback functions such as Near-End Loopback and Far-End-Loopback are supported in addition to proprietary Loopback implementations for functional testing.\r\n \r\n SMS6000 does not require any external Loop filter capacitor(s) for clock Synthesis PLL or Clock recovery circuitry making it immune to PCB related noise typically encountered, and provides a completely integrated solution. """ "overview_cn" => "" "partnumber" => "SMS6000" "priority" => 13 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 55 "provider.name" => "Soft Mixed Signal Corp." "provider.object" => "{"id":55,"name":"Soft Mixed Signal Corp.","providerslug":"soft-mixed-signal-corp"}" "provider.priority" => 121 "provider.slug" => "soft-mixed-signal-corp" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.</li>\r\n \t<li>It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, Comma detect for 8B/10B encoded data and Frame alignment functionalities.</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "Serial ATA (SATA) PHY Transceiver IP" "shortdescription_cn" => "" "slug" => "serial-ata-sata-i-ii-phy-ip-core" "sortable_id" => 679 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SMS6000 Serial ATA (SATA) PHY Transceiver IP Soft Mixed Signal Corp." "text_low_priority" => """ SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling. It contains all necessary Clock synthesis Recovery Serializer Deserializer Comma detect for 8B/10B encoded data Frame alignment functionalities. Digital controller interface realized with 10-bit parallel operation (Optional 20-bit Interface) allows use of 150 MHz (300 MHz) reference Clock. The includes Signal Detect COMRESET/COMINIT COMWAKE Out-of-Band capability compliant Specification requirements in addition to COMSAS Out-of-band detection required by Attached SCSCI (SAS).\r\n \r\n SMS6000 complies latest version SAPIS standard both as PHY Core IP discrete Transceiver implementations.\r\n \r\n SMS6000 implements full 1.0a specification terms Power Management Loopback functionality. Both Partial Slumber power management modes are supported digital portion AFE maximum efficiency. Also functions such Near-End Far-End-Loopback proprietary implementations functional testing.\r\n \r\n SMS6000 does not require any external Loop filter capacitor(s) clock Synthesis PLL or recovery circuitry making it immune PCB related noise typically encountered provides completely solution. \r\n \tSupports 1.5 Gb/s (Gen 1) 3.0 2) serial rate\r\n \tCompatible II\r\n \tUtilizes transmit receive data\r\n \tData from stream on SATA bus\r\n \tOptional 8b/10b encode/decode error indication\r\n \tNear-End Far-End Loop-back Support\r\n \tEmbedded Bit Error Rate Testing Through PBRS generation detection\r\n \tSupports HOST DEVICE applications\r\n \tOOB Detection COMSAS\r\n \tCOMMA & Squelch Support\r\n \tPower Support PM Modes.\r\n \tCalibrated Internal RX TX Termination Resistors\r\n \tSupport SCSI SAS Mode\r\n \tCompliant Interface (SAPIS)\r\n \tFull cost Implementation\r\n """ "text_medium_priority" => "SATA Serial ATA IO PHY IP Transceiver SAS " "updated_at" => 1746209957 ] "highlight" => [] "highlights" => [] ] 1 => array:3 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/22287/icon_sata-sas-3-0-transceiver-ip-with-pma-and-pcs-layer-67d687a290281.jpg.webp" "category.id" => array:2 [ 0 => 34 1 => 287 ] "category.name" => array:2 [ 0 => "SATA PHY IP" 1 => "Voltage Regulator IP" ] "category.slug" => [] "created_at" => 1740700800 "id" => "22287" "keyfeatures" => """ <ul><li>Highly customizable PMA configuration (controlled by PCS), X4 per Quad</li>\n <li>Support SATA data rate 1.5/3/6Gbps</li>\n <li>Support SAS data rate 1.5/3/6/12Gbps</li>\n <li>Digitally-control-impedance termination resistors</li>\n <li>Built-in TX equalization and RX CTLE</li>\n <li>RX Built-in Decision Feedback Equalization</li>\n <li>Built-in Eye Opening Monitor</li>\n <li>PRBS (PRBS-7/PRBS-15/PRBS-23/PRBS-31) generator and checker</li>\n <li>Multiple Loop Back</li>\n <li>Support Non-SSC, center-spread and down-spread SSC</li>\n <li>Supports SATA OOB signaling</li>\n <li>Support IEEE 1149.1 and 1149.6(AC JTAG) boundary scan</li>\n <li>Built-in self-test(BIST) features for production</li>\n <li>Advanced, built-in diagnostics including on-chip eye monitor</li>\n <li>Independent QPLL at common for clock flexibility</li>\n <li>Supports flip-chip package</li>\n <li>Low Power Consumption</li>\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "kniulink-66bb47b0d5b89.webp" "logo2" => "kniulink-66bb47b0d5b89.webp" "name" => "asic.node" "overview" => "With sophisticated architecture and advanced technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high performance application. It is highly configurable and can be tightly integrated with the user logic or SOC resources; it can support SATA protocol with data rate 1.5/3/6Gbps, and SAS protocol with data rate 1.5/3/6/12Gbps." "overview_cn" => "" "partnumber" => "SATA/SAS 3.0" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 462 "provider.name" => "KNiulink Semiconductor Ltd." "provider.object" => "{"id":462,"name":"KNiulink Semiconductor Ltd.","providerslug":"kniulink-semiconductor-ltd"}" "provider.priority" => 141 "provider.slug" => "kniulink-semiconductor-ltd" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Highly customizable PMA configuration (controlled by PCS), X4 per Quad</li>\n <li>Support SATA data rate 1.5/3/6Gbps</li>\n <li>Support SAS data rate 1.5/3/6/12Gbps</li>\n <li>Digitally-control-impedance termination resistors</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA/SAS 3.0 transceiver IP with PMA and PCS layer" "shortdescription_cn" => "" "slug" => "sata-sas-3-0-transceiver-ip-with-pma-and-pcs-layer-ip" "sortable_id" => 22287 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:2 [ 0 => 688 1 => 3 ] "taxo2" => array:2 [ 0 => 33 1 => 537 ] "taxo3" => array:2 [ 0 => 34 1 => 287 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SATA/SAS 3.0 transceiver IP with PMA and PCS layer KNiulink Semiconductor Ltd." "text_low_priority" => """ With sophisticated architecture and advanced technology the SATA/SAS transceiver IP with PMA PCS layer is designed for low power high performance application. It highly configurable can be tightly integrated user logic or SOC resources; it support SATA protocol data rate 1.5/3/6Gbps SAS 1.5/3/6/12Gbps. Highly customizable configuration (controlled by PCS) X4 per Quad\n Support 1.5/3/6Gbps\n Support 1.5/3/6/12Gbps\n Digitally-control-impedance termination resistors\n Built-in TX equalization RX CTLE\n RX Built-in Decision Feedback Equalization\n Built-in Eye Opening Monitor\n PRBS (PRBS-7/PRBS-15/PRBS-23/PRBS-31) generator checker\n Multiple Loop Back\n Support Non-SSC center-spread down-spread SSC\n Supports OOB signaling\n Support IEEE 1149.1 1149.6(AC JTAG) boundary scan\n Built-in self-test(BIST) features production\n Advanced built-in diagnostics including on-chip eye monitor\n Independent QPLL at common clock flexibility\n Supports flip-chip package\n Low Power Consumption\n """ "text_medium_priority" => "" "updated_at" => 1742116274 ] "highlight" => [] "highlights" => [] ] 2 => array:3 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/14255/icon_usb-3-2-pcie-3-1-sata-3-2-combo-phy-ip-silicon-proven-in-umc-28hpc-66bb7642b3ba5.PNG.webp" "category.id" => array:3 [ 0 => 34 1 => 353 2 => 539 ] "category.name" => array:3 [ 0 => "SATA PHY IP" 1 => "PCI Serdes / PHY IP" 2 => "USB 3.2 PHY IP" ] "category.slug" => [] "created_at" => 1607692817 "id" => "14255" "keyfeatures" => "<ul><li>Compliant with PCIe 3.1 Base Specification</li><li>Compliant with Universal Serial Bus 3.2 Specification</li><li>Compliant with Universal Serial Bus 2.0 Specification</li><li>Compliant with UTMI 1.05 Specification</li><li>Compliant with SATA 3.2 Specification</li><li>Compliant with PIPE 4.4</li><li>Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s (PCIe)</li><li>Supported data transfer rate: 5.0 GT/s and 10.0 GT/s (USB)</li><li>Supported data transfer rate: 1.5 GT/s, 3.0 GT/s and 6.0 GT/s (SATA)</li><li>High-speed data transfer rate: 480 Mbps (USB)</li><li>Full-speed data transfer rate: 12 Mbps (USB)</li><li>Supported physical lane width: x2</li><li>Supported parallel interface: 32-bit</li><li>Supported input reference clock: 100 MHz (PCIe)</li><li>Supported input crystal clock for SRIS: 25 MHz</li><li>Support crystal-less in SATA mode</li><li>Support low power operation with configurable setting in power state:</li><li>PLL control, reference clock control, and embedded power gating control</li><li>UMC 28nm HPCP 1P9M4X2Y2R_AL=28kA (uHVT/HVT/RVT/LVT) process</li><li>Operating Voltage: 0.9V, 0.95V, 1.8V and 3.3V</li><li>Providing robust testability by low cost Build-In-</li><li>Self-Test (BIST) and near/far end loopback at analog/digital interface</li><li>Silicon Proven in UMC 28HPC</li></ul>" "keyfeatures_cn" => "<ul><li>符合PCIe 3.1基本规范\r</li><li>符合通用串行总线3.2规范\r</li><li>符合通用串行总线2.0规范\r</li><li>符合UTMI 1.05技术规范的要求\r</li><li>符合SATA 3.2规范的要求\r</li><li>符合PIPE 4.4\r</li><li>支持的数据传输速率：2.5 GT/s、5.0 GT/s和8.0 GT/s（PCIe）\r</li><li>支持的数据传输速率：5.0 GT/s和10.0 GT/s（USB）\r</li><li>支持的数据传输速率：1.5 GT/s、3.0 GT/s和6.0 GT/s（SATA）\r</li><li>高速数据传输速率：480 Mbps（USB）\r</li><li>全速数据传输速率：12 Mbps（USB）\r</li><li>受支持的物理车道宽度：x2\r</li><li>所支持的并行接口：32位\r</li><li>支持的输入参考时钟：100 MHz（PCIe）\r</li><li>支持为SRIS的输入晶体时钟： 25 MHz\r</li><li>支持在SATA模式下的无水晶模式\r</li><li>支持在功率状态下进行可配置设置的低功率操作：\r</li><li>PLL控制、参考时钟控制和嵌入式电源门控控制\r</li><li>UMC 28nm HPCP 1P9M4X2Y2R_AL=28kA（uHVT/HVT/RVT/LVT）工艺\r</li><li>工作电压： 0.9V、0.95V、1.8V、3.3V\r</li><li>通过低成本的内置-提供强大的可测试性\r</li><li>模拟/数字接口上的自检（BIST）和近/远端环回测试\r</li><li>在UMC 28HPC工艺中通过硅验证</li></ul>" "keywords" => "USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serdesip, pccie combo phy, sta combo phy, sat 3.0, sata3.1, sata 3.1, pcie3.0,pcie3.1,pipe,comb" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => "The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification with support of PIPE v4.4 interface spec, Universal Serial Bus (USB) compliant with the USB 3.2, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.2 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios." "overview_cn" => "这个PHY comboIP符合PCIe 3.1基本规范的外设组件互连快车（PCIe）、PIPE v4.4接口规范、符合USB 3.2的通用串行总线（USB）、USB 2.0（USB高速和全速）和符合SATA 3.2规范的串行ATA（SATA）规范。通过支持额外的PLL控制、参考时钟控制和嵌入式电源门控控制，实现了更低的功耗运行。此外，低功率模式设置可根据客户产品的需求进行调整，能够广泛适用于各种应用领域" "partnumber" => "USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP in 28HPC" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compliant with PCIe 3.1 Base Specification</li>\n <li>Compliant with Universal Serial Bus 3.2 Specification</li>\n <li>Compliant with Universal Serial Bus 2.0 Specification</li>\n <li>Compliant with UTMI 1.05 Specification</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC" "shortdescription_cn" => "USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP，在 UMC 28HPC 中经过硅验证" "slug" => "usb-3-2-pcie-3-1-sata-3-2-combo-phy-ip-silicon-proven-in-umc-28hpc" "sortable_id" => 14255 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:2 [ 0 => 688 1 => 7 ] "taxo2" => array:3 [ 0 => 33 1 => 58 2 => 64 ] "taxo3" => array:3 [ 0 => 34 1 => 455 2 => 538 ] "taxo4" => array:2 [ 0 => 353 1 => 539 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP in 28HPC Silicon Proven UMC T2M GmbH" "text_low_priority" => "The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification support PIPE v4.4 interface spec Universal Serial Bus (USB) the USB 3.2 2.0 (USB High-speed and Full speed) ATA (SATA) SATA Specification. Lower power consumption is achieved due to additional PLL control reference clock embedded gating control. Also since aforementioned low mode setting configurable widely applicable for various scenarios. Compliant SpecificationCompliant UTMI 1.05 4.4Supported data transfer rate: 2.5 GT/s 5.0 8.0 (PCIe)Supported 10.0 (USB)Supported 1.5 3.0 6.0 (SATA)High-speed 480 Mbps (USB)Full-speed 12 physical lane width: x2Supported parallel interface: 32-bitSupported input clock: 100 MHz crystal SRIS: 25 MHzSupport crystal-less in modeSupport operation state:PLL controlUMC 28nm HPCP 1P9M4X2Y2R_AL=28kA (uHVT/HVT/RVT/LVT) processOperating Voltage: 0.9V 0.95V 1.8V 3.3VProviding robust testability by cost Build-In-Self-Test (BIST) near/far end loopback at analog/digital interfaceSilicon Proven UMC 28HPC" "text_medium_priority" => "USB3.2 usb 3.2 phy in umc 28nm USB 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata combo serdesip pccie sta sat 3.0 sata3.1 pcie3.0 pipe" "updated_at" => 1682933429 ] "highlight" => [] "highlights" => [] ] 3 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "GLOBALFOUNDRIES" ] "asic.foundry_node" => array:1 [ 0 => "GLOBALFOUNDRIES_280" ] "asic.foundry_node_process" => array:1 [ 0 => "GLOBALFOUNDRIES_280_" ] "asic.node" => array:1 [ 0 => 280 ] "asic.node_foundry" => array:1 [ 0 => "280_GLOBALFOUNDRIES" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1723569896 "id" => "18494" "keyfeatures" => "<ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li><li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li><li>AMBA 4 AXI and ACE-Lite bus interfaces</li><li>Memory data protection and memory address parity protection</li><li>Supports ATA/TAPI-7 specification</li><li>Supports power management features</li><li>Supports BIST loop-back modes</li><li>Supports up to 8 SATA devices per controller (configurable from 1 to 8 ports)</li><li>Native command queuing, streaming, and asynchronous notification</li><li>Port multiplier support with both command-based switch (CBS) and FIS-based switching (FBS)</li><li>Optional mechanical presence switch, cold presence detect, and activity LED support</li><li>Runs latest version of Windows or Linux AHCI software drivers “out of box”</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed- \n signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications. """ "overview_cn" => "" "partnumber" => "dwc_sata6gphy_gf" "priority" => 21 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li>\n <li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li>\n <li>AMBA 4 AXI and ACE-Lite bus interfaces</li>\n <li>Memory data protection and memory address parity protection</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY in GF (40nm, 28nm)" "shortdescription_cn" => "" "slug" => "sata-6g-phy-in-gf-40nm-28nm" "sortable_id" => 18494 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_sata6gphy_gf SATA 6G PHY in GF (40nm 28nm) Synopsys Inc." "text_low_priority" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using SATA interface mass storage. complete integrated is silicon-proven includes a comprehensive suite of configurable digital controllers high-speed mixed-\n signal PHYs verification IP. By providing from single vendor lowers integration risk by ensuring that all functions work together seamlessly. designers with high-performance extremely low in power area latency. has gone through extensive in-house third-party interoperability testing products shipping volume production. As leading supplier focused on delivering high-quality strict quality measures combined an expert technical support team enable accelerate time-to-market reduce next-generation storage applications. Compliant SATA/eSATA v3.3 AHCI v1.3 PIPE v4.3 specificationsAMBA 2.0 AHB AMBA 3 AXI subsystem interfacesAMBA 4 ACE-Lite bus interfacesMemory data protection memory address parity protectionSupports ATA/TAPI-7 specificationSupports management featuresSupports BIST loop-back modesSupports up 8 devices per controller (configurable 1 ports)Native command queuing streaming asynchronous notificationPort multiplier both command-based switch (CBS) FIS-based switching (FBS)Optional mechanical presence cold detect activity LED supportRuns latest version Windows or Linux software drivers “out box” """ "text_medium_priority" => "" "updated_at" => 1724088422 ] "highlight" => [] "highlights" => [] ] 4 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "UMC" ] "asic.foundry_node" => array:3 [ 0 => "UMC_400" 1 => "UMC_280" 2 => "UMC_220" ] "asic.foundry_node_process" => array:3 [ 0 => "UMC_400_" 1 => "UMC_280_" 2 => "UMC_220_" ] "asic.node" => array:3 [ 0 => 400 1 => 280 2 => 220 ] "asic.node_foundry" => array:3 [ 0 => "400_UMC" 1 => "280_UMC" 2 => "220_UMC" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1723559420 "id" => "13018" "keyfeatures" => "<ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li><li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li><li>AMBA 4 AXI and ACE-Lite bus interfaces</li><li>Memory data protection and memory address parity protection</li><li>Supports ATA/TAPI-7 specification</li><li>Supports power management features</li><li>Supports BIST loop-back modes</li><li>Supports up to 8 SATA devices per controller (configurable from 1 to 8 ports)</li><li>Native command queuing, streaming, and asynchronous notification</li><li>Port multiplier support with both command-based switch (CBS) and FIS-based switching (FBS)</li><li>Optional mechanical presence switch, cold presence detect, and activity LED support</li><li>Runs latest version of Windows or Linux AHCI software drivers “out of box”</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed- \n signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications. """ "overview_cn" => "" "partnumber" => "dwc_sata6gphy_umc" "priority" => 21 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li>\n <li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li>\n <li>AMBA 4 AXI and ACE-Lite bus interfaces</li>\n <li>Memory data protection and memory address parity protection</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY in UMC (40nm, 28nm, 22nm)" "shortdescription_cn" => "" "slug" => "sata-6g-phy-in-umc-40nm-28nm-22nm" "sortable_id" => 13018 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_sata6gphy_umc SATA 6G PHY in UMC (40nm 28nm 22nm) Synopsys Inc." "text_low_priority" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using SATA interface mass storage. complete integrated is silicon-proven includes a comprehensive suite of configurable digital controllers high-speed mixed-\n signal PHYs verification IP. By providing from single vendor lowers integration risk by ensuring that all functions work together seamlessly. designers with high-performance extremely low in power area latency. has gone through extensive in-house third-party interoperability testing products shipping volume production. As leading supplier focused on delivering high-quality strict quality measures combined an expert technical support team enable accelerate time-to-market reduce next-generation storage applications. Compliant SATA/eSATA v3.3 AHCI v1.3 PIPE v4.3 specificationsAMBA 2.0 AHB AMBA 3 AXI subsystem interfacesAMBA 4 ACE-Lite bus interfacesMemory data protection memory address parity protectionSupports ATA/TAPI-7 specificationSupports management featuresSupports BIST loop-back modesSupports up 8 devices per controller (configurable 1 ports)Native command queuing streaming asynchronous notificationPort multiplier both command-based switch (CBS) FIS-based switching (FBS)Optional mechanical presence cold detect activity LED supportRuns latest version Windows or Linux software drivers “out box” """ "text_medium_priority" => "" "updated_at" => 1724088422 ] "highlight" => [] "highlights" => [] ] 5 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "TSMC" ] "asic.foundry_node" => array:4 [ 0 => "TSMC_160" 1 => "TSMC_70" 2 => "TSMC_120" 3 => "TSMC_280" ] "asic.foundry_node_process" => array:4 [ 0 => "TSMC_160_" 1 => "TSMC_70_" 2 => "TSMC_120_" 3 => "TSMC_280_" ] "asic.node" => array:4 [ 0 => 160 1 => 70 2 => 120 3 => 280 ] "asic.node_foundry" => array:4 [ 0 => "160_TSMC" 1 => "70_TSMC" 2 => "120_TSMC" 3 => "280_TSMC" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1723559419 "id" => "13017" "keyfeatures" => "<ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li><li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li><li>AMBA 4 AXI and ACE-Lite bus interfaces</li><li>Memory data protection and memory address parity protection</li><li>Supports ATA/TAPI-7 specification</li><li>Supports power management features</li><li>Supports BIST loop-back modes</li><li>Supports up to 8 SATA devices per controller (configurable from 1 to 8 ports)</li><li>Native command queuing, streaming, and asynchronous notification</li><li>Port multiplier support with both command-based switch (CBS) and FIS-based switching (FBS)</li><li>Optional mechanical presence switch, cold presence detect, and activity LED support</li><li>Runs latest version of Windows or Linux AHCI software drivers “out of box”</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed- \n signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications. """ "overview_cn" => "" "partnumber" => "dwc_sata6gphy_tsmc" "priority" => 21 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li>\n <li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li>\n <li>AMBA 4 AXI and ACE-Lite bus interfaces</li>\n <li>Memory data protection and memory address parity protection</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY in TSMC (40nm, 28nm, 16nm, 12nm, N7)" "shortdescription_cn" => "" "slug" => "sata-6g-phy-in-tsmc-40nm-28nm-16nm-12nm-n7" "sortable_id" => 13017 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_sata6gphy_tsmc SATA 6G PHY in TSMC (40nm 28nm 16nm 12nm N7) Synopsys Inc." "text_low_priority" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using SATA interface mass storage. complete integrated is silicon-proven includes a comprehensive suite of configurable digital controllers high-speed mixed-\n signal PHYs verification IP. By providing from single vendor lowers integration risk by ensuring that all functions work together seamlessly. designers with high-performance extremely low in power area latency. has gone through extensive in-house third-party interoperability testing products shipping volume production. As leading supplier focused on delivering high-quality strict quality measures combined an expert technical support team enable accelerate time-to-market reduce next-generation storage applications. Compliant SATA/eSATA v3.3 AHCI v1.3 PIPE v4.3 specificationsAMBA 2.0 AHB AMBA 3 AXI subsystem interfacesAMBA 4 ACE-Lite bus interfacesMemory data protection memory address parity protectionSupports ATA/TAPI-7 specificationSupports management featuresSupports BIST loop-back modesSupports up 8 devices per controller (configurable 1 ports)Native command queuing streaming asynchronous notificationPort multiplier both command-based switch (CBS) FIS-based switching (FBS)Optional mechanical presence cold detect activity LED supportRuns latest version Windows or Linux software drivers “out box” """ "text_medium_priority" => "" "updated_at" => 1724088422 ] "highlight" => [] "highlights" => [] ] 6 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "SMIC" ] "asic.foundry_node" => array:1 [ 0 => "SMIC_280" ] "asic.foundry_node_process" => array:1 [ 0 => "SMIC_280_" ] "asic.node" => array:1 [ 0 => 280 ] "asic.node_foundry" => array:1 [ 0 => "280_SMIC" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1723559418 "id" => "13016" "keyfeatures" => "<ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li><li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li><li>AMBA 4 AXI and ACE-Lite bus interfaces</li><li>Memory data protection and memory address parity protection</li><li>Supports ATA/TAPI-7 specification</li><li>Supports power management features</li><li>Supports BIST loop-back modes</li><li>Supports up to 8 SATA devices per controller (configurable from 1 to 8 ports)</li><li>Native command queuing, streaming, and asynchronous notification</li><li>Port multiplier support with both command-based switch (CBS) and FIS-based switching (FBS)</li><li>Optional mechanical presence switch, cold presence detect, and activity LED support</li><li>Runs latest version of Windows or Linux AHCI software drivers “out of box”</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed- \n signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications. """ "overview_cn" => "" "partnumber" => "dwc_sata6gphy_smic" "priority" => 21 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li>\n <li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li>\n <li>AMBA 4 AXI and ACE-Lite bus interfaces</li>\n <li>Memory data protection and memory address parity protection</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY in SMIC (40nm, 28nm)" "shortdescription_cn" => "" "slug" => "sata-6g-phy-in-smic-40nm-28nm" "sortable_id" => 13016 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_sata6gphy_smic SATA 6G PHY in SMIC (40nm 28nm) Synopsys Inc." "text_low_priority" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using SATA interface mass storage. complete integrated is silicon-proven includes a comprehensive suite of configurable digital controllers high-speed mixed-\n signal PHYs verification IP. By providing from single vendor lowers integration risk by ensuring that all functions work together seamlessly. designers with high-performance extremely low in power area latency. has gone through extensive in-house third-party interoperability testing products shipping volume production. As leading supplier focused on delivering high-quality strict quality measures combined an expert technical support team enable accelerate time-to-market reduce next-generation storage applications. Compliant SATA/eSATA v3.3 AHCI v1.3 PIPE v4.3 specificationsAMBA 2.0 AHB AMBA 3 AXI subsystem interfacesAMBA 4 ACE-Lite bus interfacesMemory data protection memory address parity protectionSupports ATA/TAPI-7 specificationSupports management featuresSupports BIST loop-back modesSupports up 8 devices per controller (configurable 1 ports)Native command queuing streaming asynchronous notificationPort multiplier both command-based switch (CBS) FIS-based switching (FBS)Optional mechanical presence cold detect activity LED supportRuns latest version Windows or Linux software drivers “out box” """ "text_medium_priority" => "" "updated_at" => 1724088422 ] "highlight" => [] "highlights" => [] ] 7 => array:3 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:3 [ 0 => 34 1 => 353 2 => 382 ] "category.name" => array:3 [ 0 => "SATA PHY IP" 1 => "PCI Serdes / PHY IP" 2 => "USB 3.0 PHY IP" ] "category.slug" => [] "created_at" => 1478330235 "id" => "9734" "keyfeatures" => "<ul><li>Compatible with PCIe/USB3/SATA base Specification</li><li>Fully compatible with PIPE3.1 interface specification</li><li>Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application</li><li>Support 16-bit or 32-bit parallel interface when encode/decode enabled</li><li>Support 20-bit parallel interface when encode/decode bypassed</li><li>Support flexible reference clock frequency</li><li>Support 100MHz differential reference clock input or output (optional with SSC) in PCIe Mode</li><li>Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm</li><li>Support programmable transmit amplitude and De-emphasis</li><li>Support TX detect RX function in PCIe and USB3.0 Mode</li><li>Support Beacon signal generation and detection in PCIe Mode</li><li>Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode</li><li>Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode</li><li>Support L1 sub-state power management</li><li>Support RX low latency mode in SATA operation mode</li><li>Support Loopback BERT and Multiple Pattern BIST Mode</li><li>HPC Plus 0.9V/1.8V 1P8M</li><li>ESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mA</li><li>Silicon Proven in TSMC 28HPC+</li></ul>" "keyfeatures_cn" => "<ul><li>兼容PCIe/USB3/SATA基本规范\r</li><li>完全兼容PIPE3.1接口规范\r</li><li>数据速率可配置为1.5G/2.5G/5G/5G/6G，适用于不同的应用\r</li><li>启用编码/解码时，支持16位或32位并行接口\r</li><li>当绕过编码/解码时，支持20位并行接口\r</li><li>支持灵活的参考时钟频率\r</li><li>在PCIe模式下支持100MHz差分参考时钟输入或输出（SSC可选）\r</li><li>支持从5000ppm到0ppm的扩频时钟（SSC）生成和接收\r</li><li>支持可编程传输幅度和去加重\r</li><li>支持PCIe和USB3.0模式下的TX检测RX功能\r</li><li>支持PCIe模式下的信标信号生成和检测\r</li><li>支持USB3.0模式下的低频周期信号（LFPS）生成和检测\r</li><li>支持SATA模式下的COMWAKE、COMINIT和COMRESET（OOB）生成和检测\r</li><li>支持L1子状态电源管理\r</li><li>在SATA操作模式下支持RX低延迟模式\r</li><li>支持环回BERT和多模式BIST模式\r</li><li>HPC Plus 0.9V/1.8V 1P8M\r</li><li>ESD：HBM/MM/CDM/闭锁2000V/200V/500V/100mA\r</li><li>硅在台积电22ULP中得到验证</li></ul>" "keywords" => "USB 3.0combo PHY, SATA 3.0, PCIe2.0, combo serdes, combo phy ip, usb combo phy in tsmc,USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serdesip" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => """ The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) compliant with the PCIe 2.0 Base Specification with compatibility for the PIPE interface spec, and a USB compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed). Lower power usage is achieved by supporting more PLL control, reference clock control, and internal power gating control. Additionally, because the aforementioned low power mode option is configurable, the PHY is widely applicable for a variety of situations under different considerations of power consumption. \n \n """ "overview_cn" => "PHY组合包括符合SATA 3.0规范的串行ATA（SATA）、符合支持PIPE接口规范的PCIe 2.0基本规范的外围组件互连高速（PCIe）以及符合USB 3.0、USB 2.0（USB高速和全速）的通用串行总线（USB）。结合诸如PLL控制、参考时钟控制和内置功率门控控制之类的附加功能可减少功率使用。此外，由于上述可定制的低功率模式设置，PHY适用于具有不同功耗需求的各种情况。" "partnumber" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 28HPC+" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compatible with PCIe/USB3/SATA base Specification</li>\n <li>Fully compatible with PIPE3.1 interface specification</li>\n <li>Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application</li>\n <li>Support 16-bit or 32-bit parallel interface when encode/decode enabled</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+" "shortdescription_cn" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP，在 TSMC 28HPC+ 中经过硅验证" "slug" => "usb-3-0-pcie-2-0-sata-3-0-combo-phy-ip-silicon-proven-in-tsmc-28hpc" "sortable_id" => 9734 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:2 [ 0 => 688 1 => 7 ] "taxo2" => array:3 [ 0 => 33 1 => 58 2 => 64 ] "taxo3" => array:3 [ 0 => 34 1 => 455 2 => 381 ] "taxo4" => array:2 [ 0 => 353 1 => 382 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 28HPC+ Silicon Proven TSMC T2M GmbH" "text_low_priority" => """ The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification Peripheral Component Interconnect Express (PCIe) PCIe 2.0 Base compatibility for PIPE interface spec and USB (USB High-speed Full speed). Lower power usage is achieved by supporting more PLL control reference clock internal gating control. Additionally because aforementioned low mode option configurable widely applicable variety situations under different considerations consumption.\n \n Compatible PCIe/USB3/SATA base SpecificationFully compatible PIPE3.1 specificationData rate to 1.5G/2.5G/3G/5G/6G applicationSupport 16-bit or 32-bit parallel when encode/decode enabledSupport 20-bit bypassedSupport flexible frequencySupport 100MHz differential input output (optional SSC) in ModeSupport Spread-Spectrum (SSC) generation receiving from 5000ppm 0ppmSupport programmable transmit amplitude De-emphasisSupport TX detect RX function USB3.0 Beacon signal detection Low Frequency Periodic Signaling (LFPS) COMWAKE COMINIT COMRESET (OOB) L1 sub-state managementSupport latency operation modeSupport Loopback BERT Multiple Pattern BIST ModeHPC Plus 0.9V/1.8V 1P8MESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mASilicon Proven TSMC 28HPC+ """ "text_medium_priority" => "USB 3.0combo PHY SATA 3.0 PCIe2.0 combo serdes phy ip usb in tsmc USB3.2 3.2 umc 28nm 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata serdesip" "updated_at" => 1721223632 ] "highlight" => [] "highlights" => [] ] 8 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "TSMC" ] "asic.foundry_node" => array:1 [ 0 => "TSMC_220" ] "asic.foundry_node_process" => array:1 [ 0 => "TSMC_220_" ] "asic.node" => array:1 [ 0 => 220 ] "asic.node_foundry" => array:1 [ 0 => "220_TSMC" ] "blockdiagram" => "" "category.id" => array:4 [ 0 => 34 1 => 279 2 => 353 3 => 382 ] "category.name" => array:4 [ 0 => "SATA PHY IP" 1 => "PCI Express Phy IP" 2 => "PCI Serdes / PHY IP" 3 => "USB 3.0 PHY IP" ] "category.slug" => [] "created_at" => 1611055703 "id" => "14384" "keyfeatures" => "<ul><li>Compatible with PCIe/USB3/SATA base Specification</li><li>Fully compatible with PIPE3.1 interface specification</li><li>Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application</li><li>Support 16-bit or 32-bit parallel interface when encode/decode enabled</li><li>Support 20-bit parallel interface when encode/decode bypassed</li><li>Support flexible reference clock frequency</li><li>Support 100MHz differential reference clock input or output (optional with SSC) in PCIe Mode</li><li>Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm</li><li>Support programmable transmit amplitude and De-emphasis</li><li>Support TX detect RX function in PCIe and USB3.0 Mode</li><li>Support Beacon signal generation and detection in PCIe Mode</li><li>Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode</li><li>Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode</li><li>Support L1 sub-state power management</li><li>Support RX low latency mode in SATA operation mode</li><li>Support Loopback BERT and Multiple Pattern BIST Mode</li><li>HPC Plus 0.9V/1.8V 1P8M</li><li>ESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mA</li><li>Silicon Proven in TSMC 22ULP.</li></ul>" "keyfeatures_cn" => "<ul><li>兼容PCIe/USB3/SATA基本规范\r</li><li>完全兼容PIPE3.1接口规范\r</li><li>可为不同的应用程序调节数据速率，数据速率可配置为1.5G/2.5G/3G/5G/6G\r</li><li>当启用编码/解码时，支持16位或32位并行接口\r</li><li>当绕过编码/解码时，支持20位并行接口\r</li><li>支持灵活的参考时钟频率\r</li><li>在PCIe模式下支持100MHz差分参考时钟输入或输出（SSC可选）\r</li><li>支持扩频时钟（SSC）的生成和接收从5000ppm到0ppm\r</li><li>支持可编程的发射振幅和失重功能\r</li><li>支持在PCIe和USB3.0模式下的TX检测RX功能\r</li><li>支持在PCIe模式下的信标信号的产生和检测\r</li><li>支持USB3.0模式下的低频周期信号（LFPS）生成和检测\r</li><li>支持SATA模式下的唤醒、通信和复位（OOB）生成和检测\r</li><li>支持L1子状态电源管理\r</li><li>支持在SATA操作模式下的RX低延迟模式\r</li><li>支持回路BERT和多模式BIST模式\r</li><li>HPC+0.9V/1.8V1P8M\r</li><li>ESD: HBM/MM/CDM/LatchUp2000V/200V/500V/100mA\r</li><li>在TSMC 22ULP工艺中通过硅验证</li></ul>" "keywords" => "USB 3, USB 3.0 combo PHY, SATA 3.0, PCIe2.0, serdes, combo phy ip, usb combo phy in tsmc, USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serde" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => """ The PHY combo comprises Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification supporting PIPE interface spec, and Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB High-speed and Full speed). Incorporating additional features such as PLL control, reference clock control, and built-in power gating control leads to reduced power usage. Moreover, the PHY is versatile for a wide range of situations with different power consumption needs due to the customizable low power mode setting mentioned above. \n """ "overview_cn" => "组个Combo PHY IP符合SATA 3.0规范的串行ATA（SATA），符合PCIe 2.0基本规范并支持PIPE接口规范PCIe，以及符合USB 3.0、USB 2.0（USB高速和全速）规范的USB。这个Combo PHY IP通过支持额外的PLL控制，参考时钟控制，和内置的电源门控控制来降低功耗。此外，这个PHY IP能够根据不同的功耗的需求进行客制化设计，拥有广泛的应用场景" "partnumber" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 22ULP" "priority" => 101 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compatible with PCIe/USB3/SATA base Specification</li>\n <li>Fully compatible with PIPE3.1 interface specification</li>\n <li>Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application</li>\n <li>Support 16-bit or 32-bit parallel interface when encode/decode enabled</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP" "shortdescription_cn" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP，在 TSMC 22ULP 中经过硅验证" "slug" => "usb-3-0-pcie-2-0-sata-3-0-combo-phy-ip-silicon-proven-in-tsmc-22ulp" "sortable_id" => 14384 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:2 [ 0 => 688 1 => 7 ] "taxo2" => array:3 [ 0 => 33 1 => 58 2 => 64 ] "taxo3" => array:4 [ 0 => 34 1 => 430 2 => 455 3 => 381 ] "taxo4" => array:3 [ 0 => 279 1 => 353 2 => 382 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP in 22ULP Silicon Proven TSMC T2M GmbH" "text_low_priority" => """ The PHY combo comprises Serial ATA (SATA) compliant with SATA 3.0 Specification Peripheral Component Interconnect Express (PCIe) PCIe 2.0 Base supporting PIPE interface spec and Universal Bus (USB) USB (USB High-speed Full speed). Incorporating additional features such as PLL control reference clock built-in power gating leads to reduced usage. Moreover the is versatile for a wide range of situations different consumption needs due customizable low mode setting mentioned above.\n Compatible PCIe/USB3/SATA base SpecificationFully compatible PIPE3.1 specificationData rate configurable 1.5G/2.5G/3G/5G/6G applicationSupport 16-bit or 32-bit parallel when encode/decode enabledSupport 20-bit bypassedSupport flexible frequencySupport 100MHz differential input output (optional SSC) in ModeSupport Spread-Spectrum (SSC) generation receiving from 5000ppm 0ppmSupport programmable transmit amplitude De-emphasisSupport TX detect RX function USB3.0 Beacon signal detection Low Frequency Periodic Signaling (LFPS) COMWAKE COMINIT COMRESET (OOB) L1 sub-state managementSupport latency operation modeSupport Loopback BERT Multiple Pattern BIST ModeHPC Plus 0.9V/1.8V 1P8MESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mASilicon Proven TSMC 22ULP. """ "text_medium_priority" => "USB 3 3.0 combo PHY SATA PCIe2.0 serdes phy ip usb in tsmc USB3.2 3.2 umc 28nm 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata serde 3.0combo serdesip" "updated_at" => 1712991652 ] "highlight" => [] "highlights" => [] ] 9 => array:3 [ "document" => array:48 [ "asic.foundry" => array:4 [ 0 => "TSMC" 1 => "GLOBALFOUNDRIES" 2 => "SMIC" 3 => "UMC" ] "asic.foundry_node" => array:4 [ 0 => "TSMC_400" 1 => "GLOBALFOUNDRIES_400" 2 => "SMIC_400" 3 => "UMC_400" ] "asic.foundry_node_process" => array:5 [ 0 => "TSMC_400_G" 1 => "TSMC_400_LP" 2 => "GLOBALFOUNDRIES_400_LP" 3 => "SMIC_400_LL" 4 => "UMC_400_LP" ] "asic.node" => array:1 [ 0 => 400 ] "asic.node_foundry" => array:4 [ 0 => "400_TSMC" 1 => "400_GLOBALFOUNDRIES" 2 => "400_SMIC" 3 => "400_UMC" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1675927054 "id" => "17388" "keyfeatures" => "<ul><li>? 6-Gbps transmission rate through standard SATA cable </li><li>? Spread-spectrum clock (SSC) generation and absorption </li><li>? Programmable down-spread (+4,980 ppm through -4,980 ppm) </li><li>? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY </li><li>? Supports 20-bit interface at 300-MHz operation for SATA 6-Gbps data rate </li><li>? Supports 20-bit interface at 150-MHz operation for SATA 3-Gbps data rate </li><li>? Supports 20-bit interface at 75-MHz operation for SATA 1.5-Gbps data rate </li><li>? Integrated PHY includes transmitter, receiver, SSC generation, PLL, digital core, and ESD </li><li>? Programmable Rx equalization </li><li>? Supports collapsing of power supplies </li><li>? Supports x1/x2 configurations </li><li>? Supports legacy Half-rate mode for power-saving </li><li>? Integrated regulator to support both 3.3-V or 2.5-V I/O power supply </li><li>? Excellent performance margin and receiver sensitivity </li><li>? Robust PHY architecture that tolerates wide process, voltage, and temperature variations </li><li>? Low-jitter PLL technology with excellent supply isolation </li><li>? IEEE 1149.6 (JTAG) boundary scan </li><li>? Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester: </li><li>? Supports 6-Gbps, 3-Gbps, and 1.5-Gbps test modes </li><li>? Advanced, built-in diagnostics including on-chip sampling scope for easy debug </li><li>? Visibility and controllability of hard macro functions through programmable registers in the design </li><li>? Overrides on all ASIC side inputs for easy debug </li><li>? Access register space through simple 16-bit parallel interface </li><li>? Access register space through JTAG port</li></ul>" "keyfeatures_cn" => "" "keywords" => "SATA 6G" "logo" => "verisyno-66bb47b55ef5f.webp" "logo2" => "verisyno-66bb47b55ef5f.webp" "name" => "asic.node" "overview" => "The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SATA 6G applications. The SATA 6G PHY sata6g_pma_xN includes all the necessary logical, geometric, and physical design files to implement complete SATA 6G physical layer capability for 6-Gbps operation, connecting a host or device controller to a SATA system. The SATA 6G PHY supports the SATA 6-Gbps protocol and data rate, and is backward-compatible with SATA Gen I and Gen II operating at 1.5-Gbps and 3.0-Gbps data rates." "overview_cn" => "" "partnumber" => "SATA 6G PHY" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 486 "provider.name" => "VeriSyno Microelectronics Co., Ltd." "provider.object" => "{"id":486,"name":"VeriSyno Microelectronics Co., Ltd.","providerslug":"verisyno-microelectronics-co-ltd"}" "provider.priority" => 1 "provider.slug" => "verisyno-microelectronics-co-ltd" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>? 6-Gbps transmission rate through standard SATA cable</li>\n <li>? Spread-spectrum clock (SSC) generation and absorption</li>\n <li>? Programmable down-spread (+4,980 ppm through -4,980 ppm)</li>\n <li>? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY" "shortdescription_cn" => "" "slug" => "sata-6g-phy" "sortable_id" => 17388 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SATA 6G PHY VeriSyno Microelectronics Co. Ltd." "text_low_priority" => "The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution designed for single-chip integration into applications. sata6g_pma_xN includes all the necessary logical geometric and physical design files to implement layer capability 6-Gbps operation connecting host or device controller system. supports protocol data rate backward-compatible with Gen I II operating at 1.5-Gbps 3.0-Gbps rates. transmission through standard cable Spread-spectrum clock (SSC) generation absorption Programmable down-spread (+4 980 ppm -4 ppm) Fully clock-forwarded transceiver interface configurable using soft PMA above hard macro Supports 20-bit 300-MHz 150-MHz 3-Gbps 75-MHz Integrated transmitter receiver SSC PLL digital core ESD Rx equalization collapsing of power supplies x1/x2 configurations legacy Half-rate mode power-saving regulator support both 3.3-V 2.5-V I/O supply Excellent performance margin sensitivity Robust architecture that tolerates wide process voltage temperature variations Low-jitter technology excellent isolation IEEE 1149.6 (JTAG) boundary scan Built-in Self-Test (BIST) features production at-speed testing on any tester: test modes Advanced built-in diagnostics including on-chip sampling scope easy debug Visibility controllability functions programmable registers in Overrides ASIC side inputs Access register space simple 16-bit parallel JTAG port" "text_medium_priority" => "SATA 6G " "updated_at" => 1712895415 ] "highlight" => [] "highlights" => [] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "*" "per_page" => 10 "q" => "*" ] "search_cutoff" => false "search_time_ms" => 5 ] 2 => array:8 [ "facet_counts" => array:7 [ 0 => array:4 [ "counts" => array:3 [ 0 => array:3 [ "count" => 1 "highlighted" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "value" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" ] 1 => array:3 [ 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=> array:3 [ "count" => 1 "highlighted" => "353" "value" => "353" ] ] "field_name" => "taxo4" "sampled" => false "stats" => array:5 [ "avg" => 367.5 "max" => 382.0 "min" => 353.0 "sum" => 735.0 "total_values" => 2 ] ] ] "found" => 3 "hits" => array:3 [ 0 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "SMIC" ] "asic.foundry_node" => array:1 [ 0 => "SMIC_280" ] "asic.foundry_node_process" => array:1 [ 0 => "SMIC_280_" ] "asic.node" => array:1 [ 0 => 280 ] "asic.node_foundry" => array:1 [ 0 => "280_SMIC" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1723559418 "id" => "13016" "keyfeatures" => "<ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li><li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li><li>AMBA 4 AXI and ACE-Lite bus interfaces</li><li>Memory data protection and memory address parity protection</li><li>Supports ATA/TAPI-7 specification</li><li>Supports power management features</li><li>Supports BIST loop-back modes</li><li>Supports up to 8 SATA devices per controller (configurable from 1 to 8 ports)</li><li>Native command queuing, streaming, and asynchronous notification</li><li>Port multiplier support with both command-based switch (CBS) and FIS-based switching (FBS)</li><li>Optional mechanical presence switch, cold presence detect, and activity LED support</li><li>Runs latest version of Windows or Linux AHCI software drivers “out of box”</li></ul>" "keyfeatures_cn" => "" "keywords" => "" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interface to mass storage. The complete, integrated solution is silicon-proven and includes a comprehensive suite of configurable digital controllers, high-speed mixed- \n signal PHYs, and verification IP. By providing a complete solution from a single IP vendor, Synopsys lowers integration risk by ensuring that all the IP functions work together seamlessly. Synopsys IP for SATA provides designers with a high-performance IP solution that is extremely low in power, area, and latency. The IP has gone through extensive in-house and third-party interoperability testing with products shipping in volume production. As a leading supplier of SATA IP, Synopsys is focused on delivering high-quality IP. The strict quality measures, combined with an expert technical support team, enable designers to accelerate time-to-market and reduce integration risk for next-generation mass storage applications. """ "overview_cn" => "" "partnumber" => "dwc_sata6gphy_smic" "priority" => 21 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications</li>\n <li>AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces</li>\n <li>AMBA 4 AXI and ACE-Lite bus interfaces</li>\n <li>Memory data protection and memory address parity protection</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY in SMIC (40nm, 28nm)" "shortdescription_cn" => "" "slug" => "sata-6g-phy-in-smic-40nm-28nm" "sortable_id" => 13016 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_sata6gphy_smic SATA 6G PHY in SMIC (40nm 28nm) Synopsys Inc." "text_low_priority" => """ The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using SATA interface mass storage. complete integrated is silicon-proven includes a comprehensive suite of configurable digital controllers high-speed mixed-\n signal PHYs verification IP. By providing from single vendor lowers integration risk by ensuring that all functions work together seamlessly. designers with high-performance extremely low in power area latency. has gone through extensive in-house third-party interoperability testing products shipping volume production. As leading supplier focused on delivering high-quality strict quality measures combined an expert technical support team enable accelerate time-to-market reduce next-generation storage applications. Compliant SATA/eSATA v3.3 AHCI v1.3 PIPE v4.3 specificationsAMBA 2.0 AHB AMBA 3 AXI subsystem interfacesAMBA 4 ACE-Lite bus interfacesMemory data protection memory address parity protectionSupports ATA/TAPI-7 specificationSupports management featuresSupports BIST loop-back modesSupports up 8 devices per controller (configurable 1 ports)Native command queuing streaming asynchronous notificationPort multiplier both command-based switch (CBS) FIS-based switching (FBS)Optional mechanical presence cold detect activity LED supportRuns latest version Windows or Linux software drivers “out box” """ "text_medium_priority" => "" "updated_at" => 1724088422 ] "highlight" => [] "highlights" => [] ] 1 => array:3 [ "document" => array:48 [ "asic.foundry" => array:4 [ 0 => "TSMC" 1 => "GLOBALFOUNDRIES" 2 => "SMIC" 3 => "UMC" ] "asic.foundry_node" => array:4 [ 0 => "TSMC_400" 1 => "GLOBALFOUNDRIES_400" 2 => "SMIC_400" 3 => "UMC_400" ] "asic.foundry_node_process" => array:5 [ 0 => "TSMC_400_G" 1 => "TSMC_400_LP" 2 => "GLOBALFOUNDRIES_400_LP" 3 => "SMIC_400_LL" 4 => "UMC_400_LP" ] "asic.node" => array:1 [ 0 => 400 ] "asic.node_foundry" => array:4 [ 0 => "400_TSMC" 1 => "400_GLOBALFOUNDRIES" 2 => "400_SMIC" 3 => "400_UMC" ] "blockdiagram" => "" "category.id" => array:1 [ 0 => 34 ] "category.name" => array:1 [ 0 => "SATA PHY IP" ] "category.slug" => [] "created_at" => 1675927054 "id" => "17388" "keyfeatures" => "<ul><li>? 6-Gbps transmission rate through standard SATA cable </li><li>? Spread-spectrum clock (SSC) generation and absorption </li><li>? Programmable down-spread (+4,980 ppm through -4,980 ppm) </li><li>? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY </li><li>? Supports 20-bit interface at 300-MHz operation for SATA 6-Gbps data rate </li><li>? Supports 20-bit interface at 150-MHz operation for SATA 3-Gbps data rate </li><li>? Supports 20-bit interface at 75-MHz operation for SATA 1.5-Gbps data rate </li><li>? Integrated PHY includes transmitter, receiver, SSC generation, PLL, digital core, and ESD </li><li>? Programmable Rx equalization </li><li>? Supports collapsing of power supplies </li><li>? Supports x1/x2 configurations </li><li>? Supports legacy Half-rate mode for power-saving </li><li>? Integrated regulator to support both 3.3-V or 2.5-V I/O power supply </li><li>? Excellent performance margin and receiver sensitivity </li><li>? Robust PHY architecture that tolerates wide process, voltage, and temperature variations </li><li>? Low-jitter PLL technology with excellent supply isolation </li><li>? IEEE 1149.6 (JTAG) boundary scan </li><li>? Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester: </li><li>? Supports 6-Gbps, 3-Gbps, and 1.5-Gbps test modes </li><li>? Advanced, built-in diagnostics including on-chip sampling scope for easy debug </li><li>? Visibility and controllability of hard macro functions through programmable registers in the design </li><li>? Overrides on all ASIC side inputs for easy debug </li><li>? Access register space through simple 16-bit parallel interface </li><li>? Access register space through JTAG port</li></ul>" "keyfeatures_cn" => "" "keywords" => "SATA 6G" "logo" => "verisyno-66bb47b55ef5f.webp" "logo2" => "verisyno-66bb47b55ef5f.webp" "name" => "asic.node" "overview" => "The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SATA 6G applications. The SATA 6G PHY sata6g_pma_xN includes all the necessary logical, geometric, and physical design files to implement complete SATA 6G physical layer capability for 6-Gbps operation, connecting a host or device controller to a SATA system. The SATA 6G PHY supports the SATA 6-Gbps protocol and data rate, and is backward-compatible with SATA Gen I and Gen II operating at 1.5-Gbps and 3.0-Gbps data rates." "overview_cn" => "" "partnumber" => "SATA 6G PHY" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 486 "provider.name" => "VeriSyno Microelectronics Co., Ltd." "provider.object" => "{"id":486,"name":"VeriSyno Microelectronics Co., Ltd.","providerslug":"verisyno-microelectronics-co-ltd"}" "provider.priority" => 1 "provider.slug" => "verisyno-microelectronics-co-ltd" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>? 6-Gbps transmission rate through standard SATA cable</li>\n <li>? Spread-spectrum clock (SSC) generation and absorption</li>\n <li>? Programmable down-spread (+4,980 ppm through -4,980 ppm)</li>\n <li>? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "SATA 6G PHY" "shortdescription_cn" => "" "slug" => "sata-6g-phy" "sortable_id" => 17388 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 688 ] "taxo2" => array:1 [ 0 => 33 ] "taxo3" => array:1 [ 0 => 34 ] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SATA 6G PHY VeriSyno Microelectronics Co. Ltd." "text_low_priority" => "The SATA 6G PHY is a complete mixed-signal semiconductor intellectual property (IP) solution designed for single-chip integration into applications. sata6g_pma_xN includes all the necessary logical geometric and physical design files to implement layer capability 6-Gbps operation connecting host or device controller system. supports protocol data rate backward-compatible with Gen I II operating at 1.5-Gbps 3.0-Gbps rates. transmission through standard cable Spread-spectrum clock (SSC) generation absorption Programmable down-spread (+4 980 ppm -4 ppm) Fully clock-forwarded transceiver interface configurable using soft PMA above hard macro Supports 20-bit 300-MHz 150-MHz 3-Gbps 75-MHz Integrated transmitter receiver SSC PLL digital core ESD Rx equalization collapsing of power supplies x1/x2 configurations legacy Half-rate mode power-saving regulator support both 3.3-V 2.5-V I/O supply Excellent performance margin sensitivity Robust architecture that tolerates wide process voltage temperature variations Low-jitter technology excellent isolation IEEE 1149.6 (JTAG) boundary scan Built-in Self-Test (BIST) features production at-speed testing on any tester: test modes Advanced built-in diagnostics including on-chip sampling scope easy debug Visibility controllability functions programmable registers in Overrides ASIC side inputs Access register space simple 16-bit parallel JTAG port" "text_medium_priority" => "SATA 6G " "updated_at" => 1712895415 ] "highlight" => [] "highlights" => [] ] 2 => array:3 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "SMIC" ] "asic.foundry_node" => array:1 [ 0 => "SMIC_140" ] "asic.foundry_node_process" => array:1 [ 0 => "SMIC_140_" ] "asic.node" => array:1 [ 0 => 140 ] "asic.node_foundry" => array:1 [ 0 => "140_SMIC" ] "blockdiagram" => "" "category.id" => array:3 [ 0 => 34 1 => 353 2 => 382 ] "category.name" => array:3 [ 0 => "SATA PHY IP" 1 => "PCI Serdes / PHY IP" 2 => "USB 3.0 PHY IP" ] "category.slug" => [] "created_at" => 1624953070 "id" => "15235" "keyfeatures" => "<ul><li>Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),</li><li>Backward compatible with 1.5Gbps, 3.0bps for SATA</li><li>Backward compatible with 2.5Gbps and 5Gbps for PCIe</li><li>Full compatible with PIPE4 interface specification</li><li>20bit/16bit selectable parallel data bus</li><li>Independent channel power down control</li><li>Programmable transmit amplitude and FFE</li><li>Implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss</li><li>Production test support is optimized through high coverage at-speed BIST and loopback</li><li>Integrated on-die termination resistors and IO Pads/Bumps</li><li>Support receiver detection, LFPS/OOB/Beacon signal generation and detection</li><li>Support Spread Spectrum clock generation(optional) and receiving</li><li>Embedded Primary & Secondary ESD Protection HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mA</li><li>Silicon Proven in SMIC 14SF+</li></ul>" "keyfeatures_cn" => "<ul><li>支持SATA3（6.0Gbps），USB3.0（5Gbps）和PCIe3（8.0Gbps），\r</li><li>向后兼容 1.5Gbps，SATA 为 3.0bps\r</li><li>向后兼容 2.5Gbps 和 5Gbps 的 PCIe\r</li><li>完全兼容 PIPE4 接口规范\r</li><li>20位/16位可选并行数据总线\r</li><li>独立的通道关断控制\r</li><li>可编程发射幅度和FFE\r</li><li>实现接收器均衡自适应CTLE和DFE，以补偿插入损耗\r</li><li>通过高覆盖率高速 BIST 和环回优化生产测试支持\r</li><li>集成片上端接电阻器和 IO 焊盘/凸块\r</li><li>支持接收器检测，LFPS / OOB /信标信号生成和检测\r</li><li>支持扩频时钟生成（可选）和接收\r</li><li>嵌入式初级和次级ESD保护HBM / MM / CDM / Latch-Up 2000V / 200V / 500V / 100mA\r</li><li>在SMIC 14SF+工艺中通过硅验证</li></ul>" "keywords" => "USB 3.0combo PHY, SATA 3.0, PCIe2.0, combo serdes, combo phy ip, usb combo phy in tsmc,USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serdesip" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => """ The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support of PIPE interface spec, Universal Serial Bus (USB) compliant with the USB 3.0, USB 2.0 (USB High-speed and Full speed) and Serial ATA (SATA) compliant with SATA 3.0 Specification. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. \n USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP is a high performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption. Combo PHY IP support multiple application including USB3.0 Super Speed (5GT/s), PCIE Gen1/Gen2/Gen3 (2.5GT/s/ 5GT/s/ 8GT/s) and SATA Gen1/Gen2/Gen3 (1.5GT/3GT/6GT) This IP includes two major blocks, PMA and PCS. PMA is an analog macro to perform serial to parallel and parallel to serial conversion. PMA includes three blocks, Transmitter, Receiver and SU (includes PLL, IVREF, etc.). PCS is a digital synthesis macro to perform PHY coding sub-layer function like 8bit/10bit, elastic buffer, comma detection and BERT loopback, it also includes a register interface to access internal control registers. """ "overview_cn" => """ 这个Combo PHY IP符合SATA 3.0规范的串行ATA（SATA），符合PCIe 2.0基本规范并支持PIPE接口规范PCIe，以及符合USB 3.0、USB 2.0（USB高速和全速）规范的USB。这个Combo PHY IP通过支持额外的PLL控制，参考时钟控制，和内置的电源门控控制来降低功耗。此外，这个PHY IP能够根据不同的功耗的需求进行客制化设计，拥有广泛的应用场景。 \r\n \r\n USB 3.0 PCIe 3.0 SATA 3.0 Combo PHY IP 是高性能 SERDES IP，专为在低功耗下执行高带宽数据通信的芯片设计。这个Combo PHY IP支持多种传输速率，包括USB3.0Super Speed（5GT/s），PCIE Gen1 /Gen2 /Gen3（2.5GT/s / 5GT/s / 8GT/s）和SATA Gen1 / Gen2 / Gen3（1.5GT / 3GT / 6GT）这个Combo PHY IP由PMA和PCS组成，PMA用于执行串行到并行和并行到串行转换的模拟宏，包括三个模块，发射器、接收器和 SU（包括 PLL、IVREF 等）；PCS是用于执行PHY编码子层功能的数字合成宏，支持如8位/10位，弹性缓冲区，逗号检测和BERT环回等功能，此外，这个Combo PHY IP的交付件还包含寄存器接口来访问内部控制寄存器。 """ "partnumber" => "USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 14SF+" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),</li>\n <li>Backward compatible with 1.5Gbps, 3.0bps for SATA</li>\n <li>Backward compatible with 2.5Gbps and 5Gbps for PCIe</li>\n <li>Full compatible with PIPE4 interface specification</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+" "shortdescription_cn" => "USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP，在 SMIC 14SF+ 中经过硅验证" "slug" => "usb-3-0-pcie-3-0-sata-3-0-combo-phy-ip-silicon-proven-in-smic-14sf" "sortable_id" => 15235 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:2 [ 0 => 688 1 => 7 ] "taxo2" => array:3 [ 0 => 33 1 => 58 2 => 64 ] "taxo3" => array:3 [ 0 => 34 1 => 455 2 => 381 ] "taxo4" => array:2 [ 0 => 353 1 => 382 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.0/ PCIe SATA 3.0 Combo PHY IP in 14SF+ Silicon Proven SMIC T2M GmbH" "text_low_priority" => """ The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification support PIPE interface spec Universal Serial Bus (USB) the USB 2.0 (USB High-speed and Full speed) ATA (SATA) SATA Specification. Lower power consumption is achieved due to additional PLL control reference clock embedded gating control. Also since aforementioned low mode setting configurable widely applicable for various scenarios under different consideration consumption.\n USB Combo IP a high performance SERDES designed chips that perform bandwidth data communication while operating at consumption. multiple application including USB3.0 Super Speed (5GT/s) PCIE Gen1/Gen2/Gen3 (2.5GT/s/ 5GT/s/ 8GT/s) (1.5GT/3GT/6GT) This includes two major blocks PMA PCS. an analog macro serial parallel conversion. three Transmitter Receiver SU (includes IVREF etc.). PCS digital synthesis coding sub-layer function like 8bit/10bit elastic buffer comma detection BERT loopback it also register access internal registers. Support SATA3(6.0Gbps) USB3.0(5Gbps) PCIe3(8.0Gbps) Backward compatible 1.5Gbps 3.0bps SATABackward 2.5Gbps 5Gbps PCIeFull PIPE4 specification20bit/16bit selectable busIndependent channel down controlProgrammable transmit amplitude FFEImplemented equalization Adaptive-CTLE DFE compensate insertion lossProduction test optimized through coverage at-speed BIST loopbackIntegrated on-die termination resistors IO Pads/BumpsSupport receiver LFPS/OOB/Beacon signal generation detectionSupport Spread Spectrum generation(optional) receivingEmbedded Primary & Secondary ESD Protection HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mASilicon Proven in SMIC 14SF+ """ "text_medium_priority" => "USB 3.0combo PHY SATA 3.0 PCIe2.0 combo serdes phy ip usb in tsmc USB3.2 3.2 umc 28nm 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata serdesip" "updated_at" => 1681285923 ] "highlight" => [] "highlights" => [] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "*" "per_page" => 10 "q" => "*" ] "search_cutoff" => false "search_time_ms" => 1 ] ]]

SATA PHY IP for SMIC

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Compare 3 SATA PHY IP for SMIC from 3 vendors (1 - 3)

SATA 6G PHY in SMIC (40nm, 28nm)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection
SATA 6G PHY
- ? 6-Gbps transmission rate through standard SATA cable
- ? Spread-spectrum clock (SSC) generation and absorption
- ? Programmable down-spread (+4,980 ppm through -4,980 ppm)
- ? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
- Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),
- Backward compatible with 1.5Gbps, 3.0bps for SATA
- Backward compatible with 2.5Gbps and 5Gbps for PCIe
- Full compatible with PIPE4 interface specification