DDR IP for SMIC
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35
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CSMC 0.13um Low Power 9track Standard Cell Library, 1.2v operating voltage
- CSMC 0.13um low power process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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CSMC 0.13um 9track Standard Cell Library, 1.2v operating voltage
- CSMC 0.13um generic process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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DDR multi PHY
- ?Compatible with JEDEC standard DDR2/DDR3/LPDDR (or Mobile DDR)/ /LPDDR2/LPDDR3 SDRAMs
- ?Operating range of 100MHz (200Mb/s) to 533MHz(1066Mb/s) in DDR2/DDR3/LPDDR2/LPDDR3 modes
- ? Operating range of DC to 200MHz in Mobile DDR mode
- ? PHY Utility Block (PUBL) component
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DDR3/2 PHY
- ? DDR2/DDR3/DDR3U/DDR3L/LVCMOS operating modes
- ? Compatible with JEDEC standard DDR2/DDR3/DDR3U/DDR3L SDRAMs
- ? Scalable performance from DDR2-667 through DDR3-1600
- ? Maximum controller clock frequency of 400MHz resulting in maximum SDRAM data rate of 1600 Mbps
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SMIC 0.13um Low Leakage 9 track Standard Cell Library,1.5v operating voltage
- SMIC 0.13um Logic 1P8M 1.2V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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SMIC 0.13um 6 track High Density Standard Cell Library - LVT,1.2v operating voltage
- SMIC 0.13um Logic 1P8M 1.2V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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SMIC 0.11um 9 track High Density Standard Cell Library - LVT,1.2v operating voltageSMIC 0.11um 9 track High Density Standard Cell Library - LVT,1.2v operating voltage
- SMIC 0.11um Mixed Signal 1P8M 1.2V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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SMIC 0.11um 9 track High Density Standard Cell Library - HVT,1.2v operating voltage
- SMIC 0.11um Mixed Signal 1P8M 1.2V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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SMIC 0.18um Low Leakage 9 track Standard Cell Library,1.8v operating voltage
- SMIC 0.18um Logic Low Lekage 1P6M 1.8V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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SMIC 0.18um 9 track Standard Cell Library,1.8v operating voltage
- SMIC 0.18um Logic 1P6M 1.8V/3.3V process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.