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Interface IP Cores for Samsung

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Compare 140 Interface IP Cores for Samsung from 9 vendors (1 - 10)
  • eDP RX PHY - 14 nm
    • The eDP RX PHY IP is a cost-effective and low-power solution that includes IO pads and ESD structures.
    • With extensive built-in self-test features, including loopback and scan, it ensures robust functionality and easy verification.
    • This hardmacro supports the eDP RX v1.4b and v1.5a standard and is commonly used for connecting a timing controller (TCON) to a host processor.
    Block Diagram -- eDP RX PHY - 14 nm
  • PCIe 5.0/6.0 PHY IP - 5nm, 4nm, 2nm
    • The PCIe 5.0/6.0 PHY IP consists of hardmacro PMA and PCS compliant with PCIe Base 5.0/6.0 specification.
    • This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
    • It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.
    Block Diagram -- PCIe 5.0/6.0 PHY IP - 5nm, 4nm, 2nm
  • PCle 4.0 PHY IP - 14nm, 8nm, 5nm, 4nm
    • The PCIe 4.0 PHY IP consists of hardmacro PMA and softmacro PCS compliant with PCIe Base 4.0 specification.
    • This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
    • It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.
    Block Diagram -- PCle 4.0 PHY IP - 14nm, 8nm, 5nm, 4nm
  • MIPI D-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
    • The MIPI D-PHY IP is a hard-macro PHY for CSI RX and DSI TX. IO pads and EDS structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low-power solution.
    Block Diagram -- MIPI D-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
  • MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
    • The MIPI C-PHY IP is a hard-macro PHY for CSI RX. IO pads and ESD structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low power solution.
    Block Diagram -- MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
    • The MIPI D-PHY/C-PHY Combo IP is a hard-macro PHY for CSI RX or DSI TX. IO pads and ESD structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low-power solution.
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
  • USB4 PHY - SS SF4X, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    Block Diagram -- USB4 PHY - SS SF4X, North/South Poly Orientation
  • PHY for PCIe 6.0 and CXL
    • Architecture optimized for HPC, AI/ML, storage, and networking
    • Ultra-long reach, low latency, and low power
    • Advanced DSP delivers unmatched performance and reliability
    • Comprehensive real-time diagnostic, monitor, and test features
    • Bifurcation support for x1, x2, x4, x8, and x16 lanes
    Block Diagram -- PHY for PCIe 6.0 and CXL
  • PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
    • Wide range of protocols that support networking, high-performance computing (HPC), and applications
    • Low-latency, long-reach, and low-power modes
    • Multi-Link PHY—mix protocols within the same macro
    • EyeSurf —non-destructive on-chip oscilloscope
    • User-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and pattern testers and monitors to measure the link performance in real time
    Block Diagram -- PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
  • USB 2.0 femtoPHY SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY SS SF5A 18 x1, OTG, North/South (vertical) poly orientation
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