PHY for PCIe 6.0 and CXL

Overview

Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems

The PHY IP for PCI Express^® (PCIe^®) 6.0 is a high-performance NRZ/PAM4 SerDes designed specifically for infrastructure and data center applications. The SerDes’s ultra-long-reach equalization and robust clock-data recovery capabilities allow it to achieve unparalleled performance and reliability. In addition, the SerDes IP features low data path latency and low power consumption, making it ideal for deployment in time-sensitive applications in high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), data communications, networking, and storage systems.

Key Features

Architecture optimized for HPC, AI/ML, storage, and networking
Ultra-long reach, low latency, and low power
Advanced DSP delivers unmatched performance and reliability
Comprehensive real-time diagnostic, monitor, and test features
Bifurcation support for x1, x2, x4, x8, and x16 lanes

Block Diagram

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

Integration Views: Verilog behavioral model, GDSII, CDL, and power models
Synthesizable RTL
DFT-Verilog netlists with SS/FF, CTL, and BSDL
Reference Verilog testbenches used for generating SoC-level VCD ATE test patterns for PHY
IBIS-AMI kit

Technical Specifications

Foundry, Node

Samsung SF5A

Maturity

Silicon proven

Samsung

Pre-Silicon: 5nm

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