Analog IP for Samsung

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Compare 41 Analog IP for Samsung from 11 vendors (1 - 10)
  • PVT SENSOR
    • SGC21713_IP007708_GF_22FDX can be used in a control loop to minimize the voltage for a given frequency or maximize frequency for a given voltage
    • Based on a group of sensors, it permits PVT and aging tracking, while allowing the identification of the actual variable that changed
    • Designed to achieve 3% overall accuracy (over Load / Line / Temp), it is specified from TJ = –40°C to +125°C.
    Block Diagram -- PVT SENSOR
  • Sleep Management Subsystem
    • Power-On-Reset
    • Programmable relaxation oscillator
    • Low Power Comparator
    Block Diagram -- Sleep Management Subsystem
  • Power Management Subsystem
    • The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
    • Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
    • The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
    Block Diagram -- Power Management Subsystem
  • Sensor Interface Subsystem
    • The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
    • Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
    • The agileSensorIF Subsystem enables easy interaction with the analog world.  
    Block Diagram -- Sensor Interface Subsystem
  • Low Power BandGap
    • The agileREF_LP consists of:  A bandgap reference core; A bandgap reference voltage generator (VREF) (Reference current outputs allow for remote reconstruction of an accurate reference voltage.) Bias current generators (IBIAS) (Temperature independent bias current generators)
    Block Diagram -- Low Power BandGap
  • 8/10-bit Analog-to-Digital Converter
    • Resolution: 8b, 10b
    • Sampling Rate (Fs): 1 Msps to 20Msps
    • Input Signal Bandwidth: Fs/2
    • SINAD1: Typ 54dB
    Block Diagram -- 8/10-bit Analog-to-Digital Converter
  • Low Power Comparator
    • The agileCMP_LP is a comparator suitable for use in any low power system. It is designed to provide a flexible range of comparison voltages suitable for many sensor interface designs.
    • The agileCMP_LP consists of a voltage reference generator and comparator set at different threshold levels for multi-level detection and the output is not latched.
    Block Diagram -- Low Power Comparator
  • 30mA 2-channel LDO voltage regulator (output voltage each channel 1.0V)
    • Samsung 28nm FD-SOI
    • 1.8V analog input voltage
    • 1.0V digital input voltage
    Block Diagram -- 30mA 2-channel LDO voltage regulator (output voltage each channel 1.0V)
  • 3.3V to 1.0V, 3.0A Step-down DC-DC converter
    • Supply voltage: 3.3V analog and 1.0V digital
    • Adjustable output voltage with trimming: 0.8V÷1.15V (1.0V typical)
    • Maximum output current up to 3A
    Block Diagram -- 3.3V to 1.0V, 3.0A Step-down DC-DC converter
  • 3.3V to 1.8V, 0.7A Step-down DC-DC converter
    • Supply voltage: 3.3V analog and 1.0V digital
    • Adjustable output voltage with trimming: 1.75V÷2.05V (1.8V typical)
    • Output current 0.7A
    • Soft start mode
    Block Diagram -- 3.3V to 1.8V, 0.7A Step-down DC-DC converter
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