Analog IP for Samsung

Compare 47 Analog IP for Samsung from 12 vendors (1 - 10)

High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP for 5G, WiFi, etc
- Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
- Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
- Small die area (< 0.05 sq mm), using a LC tank oscillator
- Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
Fractional-N PLL for Performance Computing in Samsung 14LPP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.004 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
Fractional-N PLL for Performance Computing in Samsung 8LPP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.003 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
PVT SENSOR
- SGC21713_IP007708_GF_22FDX can be used in a control loop to minimize the voltage for a given frequency or maximize frequency for a given voltage
- Based on a group of sensors, it permits PVT and aging tracking, while allowing the identification of the actual variable that changed
- Designed to achieve 3% overall accuracy (over Load / Line / Temp), it is specified from TJ = –40°C to +125°C.
Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
Power Management Subsystem
- The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
- Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
- The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.