eFPGA IP for GLOBALFOUNDRIES

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Compare 3 eFPGA IP for GLOBALFOUNDRIES from 2 vendors (1 - 3)
  • eFPGA Soft IP
    • These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
    • Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
    Block Diagram -- eFPGA Soft IP
  • Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
    • An experimental Z1010 heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs has been ported to the GlobalFoundries GF12LP process.
    • The picture below shows the full layout of the experimental architecture. The official Z1010 standard will include a different ratio of LUTs, DSPs, and BRAM.
    Block Diagram -- Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
  • eFPGA on GlobalFoundries GF12LP
    • All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.
    • The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process.
    Block Diagram -- eFPGA on GlobalFoundries GF12LP
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Semiconductor IP