Parameterizable pipelined multiplier
Overview
A fixed-point Pipelined Multiplier IP Core with parameterizable of Input width, output width as well as pipeline stages
Key Features
- Synthesizeable, technology-independent IP Core for FPGA/ASIC and SoC
- Coded with SystemVerilog
- Wrapped with AXI Stream interface
- 16-bit Fixed-Point Representation/Operation
- Suitable for DSP or Machine Learning Applications
- Parameterizable Input Width, Output Width and Pipeline Stages. It is important to note that, currently, this IP only supports 16-bit Fixed-Point Operations
- The first output appears after a 2-clock cycle latency, and its latency depends on the pipeline stages parameter
Block Diagram
Applications
- DSP, Machine Learning, Video Processing, Audio Processing
Deliverables
- Top level RTL Pipelined Multiplier (.sv)
- Top level testbench (.v)