WIDE IO2 Memory Model

Overview

WIDE IO2 Memory Model provides an smart way to verify the WIDE IO2 component of a SOC or a ASIC. The SmartDV's WIDE IO2 memory model is fully compliant with standard WIDE IO2 Specification and provides the following features. Better than Denali Memory Models.

WIDE IO2 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

WIDE IO2 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports WIDE IO2 memory devices from all leading vendors.
Supports 100% of WIDE IO2 protocol standard JESD229-2.
Supports all the WIDE IO2 commands as per the specs.
Quickly validates the implementation of the WIDE IO2 standard JESD229-2.
Support Programmable burst lengths: 4,8.
Checks for following

Check-points include power up, initialization and power off rules
State based rules, Active Command rules
Read/Write Command rules etc.,
All timing violations

Supports for All Mode registers programming.
Supports Write data Mask and data bus inversion.
Supports for GPIO Mode test access.
Supports for Post Package Repair.
Supports for Power Down features.
Supports for TRR mode.
Supports for input clock stop and frequency change.
Supports for full-timing as well as behavioral versions in one model.
Supports for all timing delay ranges in one model: min, typical and max.
Constantly monitors WIDE IO2 behavior during simulation.
Protocol checker fully compliant with WIDE IO2 Specification JESD229-2.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of WIDE IO2 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the WIDE IO2 testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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