VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_01 I/O Cell Library
Overview
VeriSilicon SMIC 0.13μm SSTL2/SSTL3 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13μm Logic 1P6M Salicide 1.3V/3.3V process. This library is fully compliant with JESD8-8 Stub Series Terminated Logic for 3.3V (SSTL3), JESD8-9B Stub Series Terminated Logic for 2.5V (SSTL2) and JESD79E DDR SDRAM specification.
Key Features
- SMIC 0.13μm Logic 1P6M Salicide 1.2V/3.3V process
- Support SSTL3 class1&class2 and SSTL2 class1
- Receiver and driver operation frequency: up to 200MHz
- Power down mode in input buffer
- Power on sequence control mode
- Programmable driver strength: SSTL3 class1&2 or SSTL2 class1
- 2kv/200v typical HBM/MM ESD immunity
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
Related IPs
- VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
- SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library
- SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library
- SMIC 0.13um Low Leakage UHD RVT_x005F_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.
- SMIC 0.13um Low Leakage high density RVT_x005F_x000D_ Logic standard cell library.
- SMIC 0.13um Generic UHD RVT_x005F_x000D_ Logic standard cell library.