VeriSilicon SMIC 0.13μm SSTL2/SSTL18 Combo I/O Cell Library developed by VeriSilicon is optimized
for Semiconductor Manufacturing International Corporation (SMIC) 0.13μm Logic 1P8M Salicide
1.2V/3.3V process. This library is fully compliant with the JESD79F DDR SDRAM specification and
JESD79_2E DDR2 SDRAM specification.
VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
Overview
Key Features
- SMIC 0.13um Logic 1P8M Salicide 1.2V/3.3V process
- Suitable for six, seven and eight metal layers’ physical design
- 35um/70um nominal pad pitch for stagger/linear application
- Support SSTL2 and SSTL18
- I/O supply voltage: 1.8v VDDQ for SSTL18 and 2.5v VDDQ for SSTL2
- Clock frequency: up to 200MHz for DDR and up to 400MHz for DDR2
- Built-in adjustable On Die Termination (ODT) Resistor: 50/75/150Ohm
- Off-Chip Driver (OCD) Calibration with programmable output impedance
- 2kv/200v typical HBM/MM ESD immunity
- More details, please go to below website to contact VeriSilicon location sales:http://www.verisilicon.com/en/contactus.asp
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
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