VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O (05) Library

Overview

Key Features

• GSMC 0.18um Logic 1P6M Salicide 1.8V/3.3V process
• Supports a broad range of IO power supply from 1.62V to 3.3V
• Supports power-on sequence control
• Supports to selectively enable both input and output
• Supports open-drain I/O with low-leakage design
• Supports clock buffer for small swing signal transmission
• Supports configurable output driving capability (i.e., from 2mA ~16mA at 3.3V power supply) with selective slew rate control
• Supports configurable pull up and pull down resistor
• Supports programmable CMOS or Schmitt input threshold voltage
• Suitable for four, five, or six metal layers of physical design
• Easy interface with VeriSilicon GSMC 0.18um process standard I/O libraries

Deliverables

• Databook in electronic form
• Verilog models and Synopsys synthesis models
• Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist

Technical Specifications