USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
Overview
The USB2.0 OTG PHY is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design usage. The USB2.0 OTG PHY supports the USB2.0 480-Mbps protocol and data rate, and is backward compatible with the USB 1.1 1.5-Mbps and 12-Mbps protocol and data rates.
Key Features
- Supports High-speed, Full-Speed and Low-Speed data rates
- Supports Host, Peripherals and OTG application
- Fully Compliant with UTMI + Level 3 Specification
- Supports internal PLL for High-Speed(480MHz) Clock and Data Recovery operation
- Support Built in Self-Test(BIST) for production testing
- Including digital and analog loop back test for HS/FS/LS mode to facilitate testing and debugging
- Integrated Termination Resistors (50?, 1.5K, 15K) with auto calibration to meet high accuracy
- Support 8-bit 60MHz and 16-bit 30MHz parallel interface
- Clock and Data Recovery implemented fully by adjustable digital with edge detection to maximizing noise filtering for various applications
- Area and power consumption advantage over competitors
Deliverables
- Datasheet
- User’s Manual
- Package/PCB guideline
- SDK (standard design kit) including verilog model, .lib/.db file, .lef file
Technical Specifications
Foundry, Node
28HK/55LL
Maturity
Silicon Testing
Availability
Developing
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