The USB 2.0 Vera RVM VIP is fully documented, off the shelf component for the Verification of the USB 2.0 compliant Function Controller.
USB 2.0 Vera RVM VIP can work in a standalone mode i.e. can be plugged with any Function Controller with standard pinouts without disturbing the structure.
This VIP is developed using the Synopsys’ Vera Reuse Verification Methodology that is used in dynamic simulation of USB 2.0 based design.
The VIP provides a fast, accurate way to simplify and speed-up the device verification task. In a complex design process, verification may take up to 70% of the development time. USB 2.0 Vera RVM VIP speeds up the verification process providing a compelling cost and time to market.
Object Oriented Programming approach plays one of the key roles to achieve these goals. Writing a reusable code makes it easy for the Verification Engineer to apply the same tasks in various modules from project to project.
Product Specifications
- The VIP can work with 8-bit or 16-bit standard USB devices.
- Error Injection Mechanism, which can be turned ON or OFF for a given simulation run. Incorporated around 45+ scenarios for different Error types.
- Provides a choice for RESETTING to either High-Speed or Full-Speed mode upon startup.
- Supports RESET / SUSPEND / RESUME. On-the-fly Reset switch over from High-Speed to Full-Speed or vice-versa supported.
Layered Architecture :
In the RVM Test Environment, each layer provides a set of services to the upper layers, while abstracting it from the lower level details.
Signal Layer : This layer provides Signal-Level Connectivity in the physical representation of the DUT. This layer provides Signal Name Abstraction and connectivity to the event driven world of most simulation engines.
Command Layer : The Command Layer typically contains Bus-Functional Models, Physical-Level Drivers and Monitors associated with the various Interfaces and Physical-Level Protocols present in the DUT. It provides a consistent, Low-Level Transaction Interface to the DUT, regardless of how the DUT is modeled.
Functional Layer : The Functional Layer provides the necessary Abstraction Layers to process Application-Level Transactions and verify the correctness of the DUT.
Test Layer : Test Layer provides additional testcase-specific self-checking not provided by the Functional Layer at the Transaction Level. It can also perform checks where correctness depends on timing with respect to a particular Synchronization Event introduced by the testcase.
