UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library
Overview
UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library
Technical Specifications
Foundry, Node
UMC 55nm
Maturity
Silicon proven, Formal release
UMC
Pre-Silicon:
55nm
Related IPs
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
- UMC 40nm LP/RVT Logic Process 1.8V/2.5V/3.3V multi-voltage generic POC BOAC I/O cell library
- 28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library
- UMC 28nm Logic and Mixed-Mode HPC Processs Multi-Voltage BOAC SD3.0 I/O Cell library
- 28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library
- 0.9V/1.2V I/O Library in TSMC 55nm