UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
Overview
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
Technical Specifications
Foundry, Node
UMC 55nm eNVM EFLASH/EE2PROM/uLP-SPLIT_GATE
UMC
Pre-Silicon:
55nm
Related IPs
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
- UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
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