UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
Overview
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
Technical Specifications
Short description
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
Vendor
Vendor Name
Foundry, Node
UMC 40nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- Single Port SRAM Compiler IP, UMC 65nm SP process
- LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process
- 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process
- MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF
- MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF
- MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, write assist, supports process FF/FF+