The S5 Series offers 64-bit RISC-V performance with 32-bit power and area
Overview
The S5 Series offers 64-bit RISC-V performance with 32-bit power and area. The S5 core has a 5-6 stage pipeline, offering a great balance between performance and efficiency.
Key Features
- Up to 8 coherent S5 Cores and optional L2 Cache Controller
- Configurable core performance
- Double precision Floating Point Unit
- Level 1 Memory System and ECC
- Number, type, and width of bus interfaces
- Support for SiFive Insight Advanced Trace and Debug
Applications
- Consumer Electronics
- Motor Control
- Industrial Automation
- Storage
- High-performance embedded
Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
Technical Specifications
Maturity
Now
Related IPs
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