STS-1/3 Framer

Key Features

• Single Core SONET STS-1/3TS-3 Framer Interface giving bandwidth of 51.84 / 155.52 Mbps.
• Provides access to internal registers through a Control Interface.
• Performs Byte & Frame alignment on the Receive signal.
• Generates Frame Co-ordinates (N, row, column) for path processing. Accepts external synchronization pulse for the transmit start of frame.
• Inserts the Framing Bytes (A1,A2) and Section Trace J0 Byte or STS-1 ID (C1).
• Optionally inserts the section & line data communication channels (D1-D3) or (D4 %96 D12)
• Optionally inserts register programmable APS Byte failure (K1,K2) and synchronization status S1 Bytes.
• Computes & inserts section BIP-8 (B1), line BIP-8 (B2), path BIP-8 (B3) and Path Far End Block Error FEBE (G1).
• Optionally scrambles the Transmit Frame data and optionally descrambles the receive frame data.

Benefits

• Targeted FPGA Xilinx Virtex (2V250fg256) for STS-1

Deliverables

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL Core.
• Test Bench (Environment Variable: Verilog)

Technical Specifications