SMIC 110nm MIPI DPHY
Overview
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both Master and Slave side. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 and DSI physical layers.
Key Features
- Process:SMIC 110nm Process
- SMIC 110nm 1.2V/3.3V
- Compliant with the MIPI D-PHY spec v1.2
- Data rate per lane: High-Speed mode 80M~1.5Gbps, Low-Power mode 10Mbps
- Lane number: 1 clock + 4 data
- On-chip differential 100? terminations with calibration
Technical Specifications
Foundry, Node
SMIC, 110nm
Maturity
Pre-Silicon
SMIC
Pre-Silicon:
110nm
G
Related IPs
- MIPI DPHY Gen2 Bidirectional 4 Lanes - SMIC 28HKMG 1.8V, North/South Poly Orientation
- MIPI DPHY v1.2 Rx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
- MIPI DPHY v1.2 Tx 4 Lanes - SMIC 28PS 1.8V, North/South Poly Orientation
- MIPI DPHY Gen2 Bidirectional 2 Lanes - SMIC 40LL 2.5V
- MIPI DPHY Gen2 Bidirectional 4 Lanes - SMIC 40LL 2.5V
- MIPI DPHY Gen2 Rx-Only 2 Lanes - SMIC 40LL 2.5V