SMIC 0.18um LVDS Transceiver/Receiver
Overview
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS. The data rate between of them can be up to 700Mhz. The LVDS transceiver is implemented in SMIC 0.18um Logic process.
Key Features
- 0.18um SMIC logic process
- Operation frequency up to 700Mhz
- Integrated 100 Ohm resistor in receiver
- Do not require 1.2v reference voltage
- Power down mode available
- Compatible with TIA/EIA-644 LVDS standard
Deliverables
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II
- LVS netlist
Technical Specifications
Foundry, Node
SMIC 0.18um
Maturity
GDS ready
Availability
Now
SMIC
Pre-Silicon:
180nm
EEPROM
,
180nm
G
,
180nm
LL