Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard

Overview

Key Features

• fully compliant with the ETSI 102.613 standard
• continuous bidirectional stream through eight physical buffers: four 32 bytes buffers for automatic frame emission; four 32 bytes buffers for automatic frame reception
• 256 bytes Dual Port RAM acting as a physical buffer
• total gate count smaller than 2.3 kgates (excluding RAM)
• straightforward integration through an APB bus interface
• silicon proven in a 130 nm CMOS process
• analog front end available separately
• Master digital controller available separately

Benefits

• ETSI 102.613 compliant
• Continuous bidirectional stream
• Low gate count
• Silicon proven
• Straightforward integration

Deliverables

• VHDL source codes
• VHDL testbenches
• standalone simulation patterns
• Synopsys synthesis scripts
• design specification

Technical Specifications