VeriSilicon SMSB 0.18um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor Manufacturing Corporation (SMSB) 0.18um 1P6M Ultra Low Leakage 1.8V/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.
Silterra 0.18um ULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via ROM Compiler
Overview
Key Features
- Low Leakage
- Low Power
- High Density
- High Speed
- Automatic Power Down
- Tri-State Output(SRAM only)
- Write Mask Function(SRAM & Register File)
- More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp
Technical Specifications
Maturity
Pre-Silicon
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