SATA III HOST Controller on Virtex 6

Overview

Key Features

• Physical Layer features
• Detect OOB and COMWAKE
• Detect the K28.5 comma character and provides a 16 bit parallel output
• Power management mode handled by state machine (shared between Phy and Link layer)
• Provides error indication to upper layers
• 8b/10b encoding and decoding in Xilinx Virtex 6 GTX Macro
• Automatic Speed negotiation 3Gbs or 6Gbs
• Link Layer features
• Scrambling of tx data and descrambling of rx data
• CRC 32 calculation and check
• Report transmission status and error to Transport Layer
• Enable BIST loopback and pattern generation modes
• Auto inserted hold primitive to avoid FIFO overflow and underflow
• Partial and slumber power management modes
• CONT primitive management in receive and transmit
• The interface between the link layer and the transport layer is 32-bit wide
• Transport Layer features
• 48-bits sector address
• Programmed IO (PIO) and DMA modes
• Support BIST FIS transmission and reception
• Automatic error FIS retry capability
• Implement Shadow Registers and SATA SuperSet registers
• Simple synchronous CPU and DMA Interface for data transfers including DMA hold-off capability
• DMA interface can be connected easily to memory space or FIFOs (FIFO interface provided)
• Support DMA Abort primitive
• NCQ Support.

Deliverables

• Netlist
• Source Code

Technical Specifications