Pre-integrated IP blocks with an efficient processor and software in a single subsystem provides a configurable, SoC-ready solution that reduces design and integration effort
Overview
As more functionality is integrated into an SoC, it is costly and time consuming to develop and maintain necessary functional blocks that are complex, but are not considered differentiating technology. By pre-integrating specific IP blocks with an efficient processor and software into a single subsystem, Synopsys gives designers configurable, SoC-ready solutions that enable them to quickly implement the required embedded control functionality for their SoC.
Key Features
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
Benefits
- ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed.
- The ARChitect wizard enables drag-and-drop configuration of the core, including options for Instruction, program counter and loop counter widths
- Register file sizeTimers, reset and interrupts Byte ordering Memory type, size, partitioning, base address Power management, clock gating Ports and bus protocol Multipliers, dividers and other hardware features Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT).
- Adding/removing instructions
Technical Specifications
Maturity
Available on request
Availability
Available
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